Transistor and methods of forming integrated circuitry

Patent metadata

Field	Value
Publication number	US-11688808-B2
Application number	US-202117317674-A
Country	US
Kind code	B2
Filing date	May 11, 2021
Priority date	Aug 9, 2019
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 μm3 of one another. Other embodiments, including methods, are disclosed.

First claim

The invention claimed is:

1. A method of forming integrated circuitry, comprising: forming operative circuit components above a substrate; forming an insulator material directly above the operative circuit components; forming a bottom material, a top material, and a middle material vertically between the bottom and top materials directly above the insulator material; the bottom, top, and middle materials respectively comprising a bottom source/drain region, a top source/drain region, and a channel region vertically between the bottom and top source/drain regions in a finished construction of a transistor that will be directly above the insulator material; at least the bottom and the top materials comprising conductivity-increasing dopant therein in the finished construction of the transistor; laser annealing at least one of the bottom, top, and middle materials to melt and then crystallize the at least one of the bottom, top, and middle materials to be crystalline; the laser annealing activating the conductivity-increasing dopant that is in the at least one of the bottom, top, and middle materials; the insulator material that is vertically between the operative circuit components and the bottom material shielding the operative circuit components there-below from heat generated during the laser annealing that would otherwise render the operative circuit components to become circuit inoperative; and forming a gate insulator and a gate laterally-adjacent the middle material.

2. The method of claim 1 wherein at least some of the melting and at least some of the activating during the laser annealing occur at the same time.

3. The method of claim 2 wherein at least most of the activating occurs during the melting.

4. The method of claim 1 wherein the laser annealing comprises multiple laser shots individually comprising a pulse width of 5 to 250 nanoseconds.

5. The method of claim 1 wherein the laser annealing forms all crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region to have an average crystal size within 0.064 μm 3 of one another.

6. The method of claim 1 wherein,
the top source/drain region has a first conductivity-increasing dopant therein at a concentration rendering semiconductor material of the top source/drain region to be conductive;
the bottom source/drain region has a second conductivity-increasing dopant therein at a concentration rendering semiconductor material of the bottom source/drain region to be conductive; and
the laser annealing:
is at least of the top source/drain region;
forms an upper portion of the channel region adjacent the top source/drain region to have a non-conductive concentration of the first conductivity-increasing dopant therein; and
forms a lower portion of the channel region adjacent the bottom source/drain region to have a non-conductive concentration of the second conductivity-increasing dopant therein, the upper portion being vertically thicker than the lower portion.

7. The method of claim 1 wherein the insulator material has a minimum thickness of no less than 1,000 Angstroms.

8. The method of claim 7 wherein the insulator material has a minimum thickness of no less than 2,000 Angstroms.

9. The method of claim 8 wherein the insulator material has a minimum thickness of 2,000 Angstroms to 5,000 Angstroms.

10. The method of claim 1 wherein the insulator material comprises silicon dioxide.

11. The method of claim 1 wherein the insulator material comprises silicon nitride.

12. The method of claim 1 comprising forming at least some of the operative circuit components to comprise lower transistors individually comprising a lower top source/drain region, a lower bottom source/drain region, a lower channel region vertically between the lower top and bottom source/drain regions, and a lower gate operatively laterally-adjacent the lower channel region.

13. The method of claim 12 wherein forming the lower transistors comprises laser annealing material from which at least one of the individual lower top source/drain region, the lower bottom source/drain region, and the lower channel region is made.

Assignees

• Micron Technology Inc

Inventors

• Liu Hung-Wei
• Chhajed Sameer
• Hull Jeffery B
• Khandekar Anish A

Classifications

• H10P14/3816

  Pulsed laser beam · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3256

  Microstructure · CPC title

• H10P14/3211 Primary

  Silicon, silicon germanium or germanium · CPC title