Vertical Thin Film Transistors In Non-Volatile Storage Systems

Patent metadata

Field	Value
Publication number	US-2016284765-A1
Application number	US-201615173104-A
Country	US
Kind code	A1
Filing date	Jun 3, 2016
Priority date	Mar 3, 2014
Publication date	Sep 29, 2016
Grant date	—

Abstract

Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.

First claim

What is claimed is:

1 . A non-volatile storage system, comprising:
a global bit line; a first vertical thin film transistor (TFT) select device formed over the global bit line, the first vertical TFT select device having a first vertical sidewall and a first gate; a second vertical thin film transistor (TFT) select device formed over the global bit line, the second vertical TFT select device having a second vertical sidewall and a second gate; a dielectric base extending partially between the first vertical sidewall and the second vertical sidewall, the dielectric base having a first notch formed at a first end adjacent to the first vertical sidewall and a second notch formed at a second end adjacent to the second vertical sidewall; and a gate dielectric formed along the first vertical sidewall and separating the first gate from the first vertical sidewall, the gate dielectric formed along the second vertical sidewall and separating the second gate from the second vertical sidewall, the gate dielectric extending vertically in the first notch and the second notch such that the gate dielectric extends below a level of an upper surface of the dielectric base.

2 . The non-volatile storage system of claim 1 , wherein:
the first notch extends vertically through the dielectric base; and the second notch extends vertically through the dielectric base.

3 . The non-volatile storage system of claim 1 , wherein:
the first notch extends vertically partially through the dielectric base; and the second notch extends vertically partially through the dielectric base.

4 . The non-volatile storage system of claim 1 , wherein:
the first vertical TFT select device includes an upper S/D region coupled to an upper surface of a first body and a first vertical bit line; the first vertical TFT select device includes a lower S/D region coupled to a lower surface of the first body and the global bit line; the second vertical TFT select device includes an upper S/D region coupled to an upper surface of a second body and a second vertical bit line; and the second vertical TFT select device includes a lower S/D region coupled to a lower surface of the second body and the global bit line.

5 . The non-volatile storage system of claim 1 , wherein the global bit line is a first global bit line, the non-volatile storage system further comprises:
a monolithic three-dimensional array of memory cells positioned above the substrate; a plurality of word lines coupled to the memory cells; a plurality of global bit lines including the first global bit line; a plurality of vertical bit lines coupled to the memory cells, the plurality of vertical bit lines including a first vertical bit line coupled to the first vertical TFT select device and a second vertical bit line coupled to the second vertical TFT select device; and a plurality of vertical TFT select devices including the first vertical TFT select device and the second vertical TFT select device, the vertical TFT select devices are coupled between the vertical bit lines and the global bit lines; wherein the vertical bit lines are in communication with the global bit lines when the vertical TFT select devices are activated.

6 . A non-volatile storage system, comprising:
a global bit line; a first vertical thin film transistor (TFT) select device formed over the global bit line, the first vertical TFT select device having a first vertical sidewall and a first gate; a second vertical thin film transistor (TFT) select device formed over the global bit line, the second vertical TFT select device having a second vertical sidewall and a second gate; a dielectric base extending partially between the first vertical sidewall and the second vertical sidewall; and a gate dielectric formed along the first vertical sidewall and separating the first gate from the first vertical sidewall, the gate dielectric formed along the second vertical sidewall and separating the second gate from the second vertical sidewall, the gate dielectric extending vertically below a level of an upper surface of the dielectric base.

7 . The non-volatile storage system of claim 6 , wherein:
the gate dielectric extends vertically to a level of a lower surface of the dielectric base.

8 . The non-volatile storage system of claim 6 , wherein:
the gate dielectric extends vertically to a level above a lower surface of the dielectric base.

9 . The non-volatile storage system of claim 6 , wherein:
the gate dielectric extends vertically below the level of the upper surface of the dielectric base at a first end of the dielectric base and a second end of the dielectric base.

10 . The non-volatile storage system of claim 6 , wherein:
the first vertical TFT select device includes an upper S/D region coupled to an upper surface of a first body and a first vertical bit line; the first vertical TFT select device includes a lower S/D region coupled to a lower surface of the first body and the global bit line; the second vertical TFT select device includes an upper S/D region coupled to an upper surface of a second body and a second vertical bit line; and the second vertical TFT select device includes a lower S/D region coupled to a lower surface of the second body and the global bit line.

11 . The non-volatile storage system of claim 6 , wherein the global bit line is a first global bit line, the non-volatile storage system further comprises:
a monolithic three-dimensional array of memory cells positioned above the substrate; a plurality of word lines coupled to the memory cells; a plurality of global bit lines including the first global bit line; a plurality of vertical bit lines coupled to the memory cells, the plurality of vertical bit lines including a first vertical bit line coupled to the first vertical TFT select device and a second vertical bit line coupled to the second vertical TFT select device; and a plurality of vertical TFT select devices including the first vertical TFT select device and the second vertical TFT select device, the vertical TFT select devices are coupled between the vertical bit lines and the global bit lines; wherein the vertical bit lines are in communication with the global bit lines when the vertical TFT select devices are activated.

Assignees

• Sandisk Technologies Llc

Inventors

• Takeguchi Naoki
• Iuchi Hiroaki

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title