Display device

Patent metadata

Field	Value
Publication number	US-2017082902-A1
Application number	US-201615368969-A
Country	US
Kind code	A1
Filing date	Dec 5, 2016
Priority date	Dec 20, 2010
Publication date	Mar 23, 2017
Grant date	—

Abstract

To provide a display device in which parasitic capacitance between wirings can be reduced while preventing increase in wiring resistance. To provide a display device with improved display quality. To provide a display device with low power consumption. A pixel of the liquid crystal display device includes a signal line, a scan line intersecting with the signal line, a first electrode projected from the signal line, a second electrode facing the first electrode, and a pixel electrode connected to the second electrode. Part of the scan line has a loop shape, and part of the first electrode is located in a region overlapped with an opening of the scan line. In other words, part of the first electrode is not overlapped with the scan line.

First claim

1 . (canceled)

2 . A display device comprising:
a transistor; a capacitor electrically connected to the transistor; a first line extending along a first direction and comprising an opening; a second line extending along a second direction, crossing the first line, and comprising a region overlapping with the opening; a third line extending along the first direction; a conductive layer made from a same material and provided in a same plane as the second line; a semiconductor film comprising a region overlapping with the first line and comprising a channel region of the transistor; a pixel electrode electrically connected to the semiconductor film; wherein the second line comprises a projection extending along the first direction, wherein the projection comprises a region overlapping with the opening, wherein the projection comprises a region that can function as a first electrode of the transistor, wherein the first line and the third line are made from a same material and provided in a same plane, wherein the third line comprises a region that can function as a first electrode of the capacitor, wherein the region of the third line overlaps with the conductive layer, and wherein the conductive layer comprises a region that can function as a second electrode of the transistor and a region than can function as a second electrode of the capacitor.

3 . The display device according to claim 2 ,
wherein end portions of the semiconductor film are located on outer sides than a portion where the second line, the projection, and the conductive layer, intersect with the first line and the third line.

4 . The display device according to claim 2 ,
wherein the semiconductor film overlaps with the second line.

5 . The display device according to claim 2 ,
wherein the semiconductor film overlaps with the third line.

6 . The display device according to claim 2 ,
wherein the region of the conductive layer that can function as a second electrode of the capacitor extends along the first direction.

7 . The display device according to claim 2 ,
wherein the semiconductor film comprises a region overlapping with the opening.

8 . The display device according to claim 2 ,
wherein the semiconductor film is formed by using silicon layer.

9 . The display device according to claim 2 ,
wherein the semiconductor film is formed by using an oxide semiconductor film.

10 . A display device comprising:
a substrate; a first insulating layer over the substrate; a first transistor and a second transistor; a first capacitor and a second capacitor electrically connected to a first electrode of the first transistor and to a first electrode of the second transistor, respectively; a first capacitor wiring and a second capacitor wiring between the substrate and the first insulating layer, each of the first capacitor wiring and the second capacitor wiring extending along a first direction; a first conductive layer and a second conductive layer each over the first insulating layer; a second insulating layer over the first conductive layer and the second conductive layer; a first pixel electrode and a second pixel electrode over the second insulating layer and electrically connected to the first electrode of the first transistor and to the first electrode of the second transistor, respectively; a scan line between the substrate and the first insulating layer, the scan line extending generally along the first direction and comprising an opening; and a third conductive layer continuously formed, crossing the scan line, the first capacitor wiring, and the second capacitor wiring, and overlapping the opening; wherein the scan line, the first capacitor wiring, and the second capacitor wiring are formed from a same first material and are provided in a same first plane between the substrate and the first insulating layer, wherein the first conductive layer, the second conductive layer, and the third conductive layer are formed from a same second material and are provided in a same second plane over the first insulating layer; wherein the first transistor comprises a first portion of the scan line, the first conductive layer, and a first portion of the third conductive layer as a gate electrode, a first electrode, and a second electrode, respectively, wherein the second transistor comprises a second portion of the scan line, the second conductive layer, and a second portion of the third conductive layer as a gate electrode, a first electrode, and a second electrode, respectively, wherein the first capacitor comprises the first capacitor wiring and the first conductive layer as a first electrode and a second electrode, respectively, wherein the second capacitor comprises the second capacitor wiring and the second conductive layer as a first electrode and a second electrode, respectively, wherein the first portion of the third conductive layer and the second portion of the third conductive layer only partly overlap with the opening, wherein the first pixel electrode overlaps the first capacitor and is in direct contact with the first conductive layer via a first contact opening in the second insulating layer, the first contact opening entirely overlapping with the first capacitor wiring, and wherein the second pixel electrode overlaps the second capacitor and is in direct contact with the second conductive layer via a second contact opening in the second insulating layer, the second contact opening entirely overlapping with the second capacitor wiring.

11 . The display device according to claim 10 , further comprising a semiconductor film overlapping with a signal line comprised in the third conductive layer.

12 . The display device according to claim 10 ,
wherein the third conductive layer comprises a signal line extending along a second direction and a signal electrode extending from the signal line along the first direction, wherein the signal electrode overlaps with the opening, and wherein the signal electrode comprises the first portion and the second portion of the third conductive layer.

13 . A display device comprising:
a substrate; a first insulating layer over the substrate; a first transistor and a second transistor; a first capacitor and a second capacitor electrically connected to a first electrode of the first transistor and to a first electrode of the second transistor, respectively; a first capacitor wiring and a second capacitor wiring between the substrate and the first insulating layer, each of the first capacitor wiring and the second capacitor wiring extending along a first direction; a first conductive layer and a second conductive layer each over the first insulating layer; a second insulating layer over the first conductive layer and the second conductive layer; a first pixel electrode and a second pixel electrode over the second insulating layer and electrically connected to the first electrode of the first transistor and to the first electrode of the second transistor, respectively; a scan line between the substrate and the first insulating layer, the scan line extending generally along the first direction and comprising an opening; a first semiconductor film over the first insulating layer and below the second insulating layer and the first conductive layer, and overlapping with a first portion of the scan line; a second semiconductor film over the first insulating layer and below the second insulating layer and the second conductive layer, and overlapping with a second portion of the scan line; and a third conductive layer continuously formed, crossing the scan line, the first capacitor wirin

Assignees

• Semiconductor Energy Lab

Inventors

• Hirose Atsushi

Classifications

• G02F1/136277

  formed on a semiconductor substrate, e.g. of silicon · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G02F2202/10

  semiconductor · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title