Display substrate, display panel, and display device

Patent metadata

Field	Value
Publication number	US-11676532-B2
Application number	US-202017434119-A
Country	US
Kind code	B2
Filing date	Nov 13, 2020
Priority date	Nov 13, 2020
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A display substrate, a display panel, and a display device are provided. The display substrate includes: a base substrate; a plurality of sub-pixels in the display pixel region, wherein each sub-pixel includes a pixel driving circuit; a plurality of first dummy sub-pixel structures on the base substrate and in the first dummy pixel region, wherein at least one first dummy sub-pixel structure includes a compensation capacitor; and a plurality of scan signal lines arranged on the base substrate and configured to transmit a scan signal to the pixel driving circuit. At least one scan signal line extends through the display pixel region and the first dummy pixel region, and the at least one scan signal line is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels and is further electrically connected to the compensation capacitor of the at least one first dummy sub-pixel structure.

First claim

What is claimed is:

1. A display substrate comprising a display pixel region, a first dummy pixel region and at least two openings, wherein the first dummy pixel region is located between the at least two openings, and wherein the display substrate comprises:
a base substrate;
a plurality of sub-pixels arranged on the base substrate and located in the display pixel region, wherein the plurality of sub-pixels are arranged in an array in a first direction and a second direction, and each sub-pixel comprises a pixel driving circuit;
a plurality of first dummy sub-pixel structures arranged on the base substrate and located in the first dummy pixel region, wherein at least one first dummy sub-pixel structure comprises a compensation capacitor; and
a plurality of scan signal lines arranged on the base substrate and configured to transmit a scan signal to the pixel driving circuit, wherein at least one scan signal line extends through the display pixel region and the first dummy pixel region,
wherein the at least one scan signal line is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels, and is further electrically connected to the compensation capacitor of the at least one first dummy sub-pixel structure;
wherein the display substrate further comprises:
a first compensation connection part, wherein the compensation capacitor comprises a first compensation capacitor electrode, the first compensation connection part has one end electrically connected to the first compensation capacitor electrode and the other end electrically connected to the at least one scan signal line; and
a via hole exposing a part of the at least one scan signal line, wherein the other end of the first compensation connection part is electrically connected to the at least one scan signal line through the first via hole,
wherein the compensation capacitor further comprises a second compensation capacitor electrode, and an orthographic projection of the first compensation capacitor electrode on the base substrate at least partially overlaps an orthographic projection of the second compensation capacitor electrode on the base substrate;
wherein the second compensation capacitor electrode comprises a first through hole, and an orthographic projection of the first through hole on the base substrate falls within the orthographic projection of the first compensation capacitor electrode on the base substrate; and
wherein the display substrate further comprises a second via hole exposing a portion of the first compensation capacitor electrode, and the one end of the first compensation connection part is electrically connected to the first compensation capacitor electrode through the first through hole and the second via hole.

2. The display substrate of claim 1 , wherein the pixel driving circuit comprises at least a storage capacitor having a capacitance value less than that of the compensation capacitor.

3. The display substrate of claim 2 , wherein the storage capacitor comprises a first storage capacitor electrode and a second storage capacitor electrode, and an orthographic projection of the first storage capacitor electrode on the base substrate at least partially overlaps an orthographic projection of the second storage capacitor electrode on the base substrate; and
wherein an orthographic projection of an overlapping portion between the first compensation capacitor electrode and the second compensation capacitor electrode on the base substrate has an area greater than that of an orthographic projection of an overlapping portion between the first storage capacitor electrode and the second storage capacitor electrode on the base substrate.

4. The display substrate of claim 3 , wherein the first compensation capacitor electrode and the first storage capacitor electrode are located in a first conductive layer, and the second compensation capacitor electrode and the second storage capacitor electrode are located in a second conductive layer located on a side of the first conductive layer away from the base substrate.

5. The display substrate of claim 4 , wherein the third compensation capacitor electrode and the first compensation connection part are located in a third conductive layer located on a side of the second conductive layer away from the base substrate; and/or
wherein the third compensation capacitor electrode and the first compensation connection part are connected to each other so as to form a continuously extending integral structure.

6. The display substrate of claim 2 , wherein a size of the orthographic projection of the first compensation capacitor electrode on the base substrate in the first direction is greater than a size of the orthographic projection of the first storage capacitor electrode on the base substrate in the first direction; and/or
wherein a size of the orthographic projection of the first compensation capacitor electrode on the base substrate in the second direction is greater than a size of the orthographic projection of the first storage capacitor electrode on the base substrate in the second direction; and/or
wherein a size of the orthographic projection of the second compensation capacitor electrode on the base substrate in the first direction is greater than a size of the orthographic projection of the second storage capacitor electrode on the base substrate in the first direction; and/or
wherein a size of the orthographic projection of the second compensation capacitor electrode on the base substrate in the second direction is greater than a size of the orthographic projection of the second storage capacitor electrode on the base substrate in the second direction.

7. The display substrate of claim 6 , wherein a size of the orthographic projection of the first compensation capacitor electrode on the base substrate in the first direction is in a range of 16 microns to 30 microns; and/or
wherein a size of the orthographic projection of the first compensation capacitor electrode on the base substrate in the second direction is in a range of 16 microns to 30 microns; and/or
wherein a size of the orthographic projection of the first storage capacitor electrode on the base substrate in the first direction is in a range of 10 microns to 16 microns; and/or
wherein a size of the orthographic projection of the first storage capacitor electrode on the base substrate in the second direction is in a range of 8 microns to 15 microns; and/or
wherein a size of the orthographic projection of the second compensation capacitor electrode on the base substrate in the first direction is in a range of 23 microns to 30 microns; and/or
wherein a size of the orthographic projection of the second compensation capacitor electrode on the base substrate in the second direction is in a range of 22 microns to 30 microns; and/or
wherein a size of the orthographic projection of the second storage capacitor electrode on the base substrate in the first direction is in a range of 18 microns to 23 microns; and/or
wherein a size of the orthographic projection of the second storage capacitor electrode on the base substrate in the second direction is in a range of 10 microns to 15 microns.

8. The display substrate of claim 2 , further comprising:
a second dummy pixel region located between the first dummy pixel region and the at least two openings; and
a plurality of dummy pixels arranged on the base substrate and located in the second dummy pixel region, wherein each dummy pixel comprises at least a dummy capacitor having a capacitance value substantially equal to that of the storage capacitor.

9. The display substrate of claim 8 , wherein the dummy capacitor comprises a first dummy capacitor electrode and a second

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Mengqi
• Qing Haigang
• Li Zhengkun
• Li De
• Yi Hong
• Wang Shilong

Classifications

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2320/0238

  Improving the black level · CPC title

• G09G2320/0214

  with crosstalk due to leakage current of pixel switch in active matrix panels · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• H10K59/88

  Dummy elements, i.e. elements having non-functional features · CPC title