Display device and method for manufacturing the same
US-2015255017-A1 · Sep 10, 2015 · US
US9941169B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9941169-B2 |
| Application number | US-201615077733-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 22, 2016 |
| Priority date | Dec 23, 2013 |
| Publication date | Apr 10, 2018 |
| Grant date | Apr 10, 2018 |
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An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer. The device further includes a storage capacitor including a first capacitor electrode electrically coupled to a drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to a gate electrode of the driving thin film transistor. The device also includes an organic light emitting diode connected to the drain electrode of the driving transistor. The gate insulating layer has at least one hole in a region where the gate insulating layer overlaps the second semiconductor layer, thereby exposing the second semiconductor layer to the second capacitor electrode.
Opening claim text (preview).
What is claimed is: 1. A method of fabricating an organic light emitting diode display device, comprising: forming a first capacitor electrode over a substrate; forming a buffer layer over the first capacitor electrode; forming a first semiconductor layer and a second semiconductor layer over the buffer layer; forming a gate insulating layer over the first semiconductor layer and the second semiconductor layer; forming at least one hole in the gate insulating layer in a region where the gate insulating layer overlaps the second semiconductor layer by patterning the gate insulating layer, the hole exposing the second semiconductor layer through the gate insulating layer; forming a gate electrode on the gate insulating layer and forming a second capacitor electrode on the second semiconductor layer in the hole of the gate insulating layer, the second capacitor electrode being electrically coupled to the gate electrode; forming an inter insulating layer over the gate electrode and the second capacitor electrode; forming source and drain electrodes over the inter insulating layer, the drain electrode being electrically coupled to the first capacitor electrode; forming a passivation layer over the source and drain electrodes; and sequentially forming a first OLED electrode, an organic light emitting layer and a second OLED electrode over the passivation layer. 2. The method of claim 1 , wherein forming the source and drain electrodes includes forming a third capacitor electrode electrically connected to the drain electrode and disposed over the inter insulating layer and the second capacitor electrode prior to forming of the passivation layer. 3. The method of claim 1 , wherein forming the first capacitor electrode includes forming a light-blocking layer disposed under the first semiconductor layer and electrically connected to the gate electrode. 4. The method of claim 1 , wherein forming the second capacitor electrode includes forming a connection pattern between the drain electrode and the first capacitor electrode.
of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title
Interconnections, e.g. scanning lines · CPC title
comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title
of multiple TFTs · CPC title
Manufacture or treatment · CPC title
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