Selectable vias for back end of line interconnects

Patent metadata

Field	Value
Publication number	US-11670588-B2
Application number	US-201916243790-A
Country	US
Kind code	B2
Filing date	Jan 9, 2019
Priority date	Jan 9, 2019
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

Integrated circuits including selectable vias are disclosed. The techniques are particularly well-suited to back end of line (BEOL) processes. In accordance with some embodiments, a selectable via includes a vertically-oriented thin film transistor structure having a wrap around gate, which can be used to effectively select (or deselect) the selectable via ad hoc. When a selectable via is selected, a signal is allowed to pass through the selectable via. Conversely, when the selectable via is not selected, a signal is not allowed to pass through the selectable via. The selectable characteristic of the selectable via allows multiple vias to share a global interconnect. The global interconnect can be connected to any number of selectable vias, as well as standard vias.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a plurality of first interconnect features;
a plurality of second interconnect features;
a third interconnect feature;
a first plurality of selectable vias, each of the first plurality of selectable vias comprising a corresponding first thin film transistor (TFT) structure, the first TFT structure including a first gate electrode, a first source contact, and a first drain contact, wherein one of the first source contact or the first drain contact is connected to a corresponding one of the plurality of first interconnect features, and the other one of the first source contact or the first drain contact is connected to the third interconnect feature, and the first gate electrode is configured to receive a first select signal that causes the corresponding one of the plurality of first interconnect features to be electrically connected to the third interconnect feature; and
a second plurality of selectable vias, each of the second plurality of selectable vias comprising a second thin film transistor (TFT) structure, the second TFT structure including a second gate electrode, a second source contact, and a second drain contact, wherein one of the second source contact or the second drain contact is connected to a corresponding one of the plurality of second interconnect features, and the other one of the second source contact or the second drain contact is connected to the third interconnect feature, and the second gate electrode is configured to receive a second select signal that causes the corresponding one of the plurality of second interconnect features to be electrically connected to the third interconnect feature, wherein the third interconnect feature vertically overlaps and extends between the other one of the second source contact or the second drain contact of each of the second TFT structures and the other one of the first source contact or the first drain contact of each of the first TFT structures, and wherein the third interconnect feature electrically couples the other one of the second source contact or the second drain contact of each of the second TFT structures and the other one of the first source contact or the first drain contact of each of the first TFT structures.

2. The integrated circuit structure of claim 1 , wherein the first source contact and the first drain contact are oriented in a first vertical configuration, and the second source contact and the second drain contact are oriented in a second vertical configuration.

3. The integrated circuit structure of claim 1 , wherein the first and second pluralities of interconnect features are part of a local interconnect structure, and the integrated circuit structure further comprises a device layer adjacent the local interconnect, the device layer including first and second non-planar transistors, the first and second interconnect features each connected to the one or both of the first and second non-planar transistors.

4. The integrated circuit structure of claim 3 , wherein the third interconnect feature is included in an interconnect layer above the device layer and the local interconnect structure.

5. The integrated circuit structure of claim 1 , wherein each of the first and second TFT structures comprises a transition metal dichalcogenide (TMD) material.

6. The integrated circuit structure of claim 1 , wherein each of the first TFT structures further comprises a first gate dielectric, the first gate dielectric disposed between the first gate electrode and a first channel structure, and each of the second TFT structures further comprises a second gate dielectric, the second gate dielectric disposed between the second gate electrode and a second channel structure, and wherein the first gate dielectric wraps around the first channel structure and the first gate electrode wraps around the first gate dielectric, and the second gate dielectric wraps around the second channel structure and the second gate electrode wraps around the second gate dielectric.

7. An integrated circuit structure, comprising:
a first layer comprising a plurality of interconnects within insulator material, the plurality of interconnects including at least a first plurality of interconnects and a second plurality of interconnects;
a second layer above the first layer, the second layer including a first plurality of selectable vias and a second plurality of selectable vias, each selectable via of the first plurality of selectable vias including a first selectable via comprising a first thin film transistor (TFT) structure, and each selectable via of the second plurality of selectable vias comprising a second TFT structure, wherein each first selectable via is connected to a corresponding one of the first plurality of interconnects, and each second selectable via is connected to a corresponding one of the second plurality of interconnects; and
a third layer above the second layer, the third layer comprising a global interconnect, wherein the global interconnect vertically overlaps and extends between each of the first selectable vias and each of the second selectable vias, and wherein the global interconnect electrically couples each of the first selectable vias and each of the second selectable vias.

8. The integrated circuit structure of claim 7 , wherein source and drain contacts for each of the first and second TFT transistor structures are oriented in a vertical configuration.

9. The integrated circuit structure of claim 7 , wherein the first and second pluralities of interconnects are part of a local interconnect structure, and the integrated circuit structure further comprises a device layer adjacent the local interconnect, the device layer including first and second non-planar transistors, the first and second pluralities of interconnects each connected to the one or both of the first and second non-planar transistors.

10. The integrated circuit structure of claim 9 , wherein the global interconnect is further connected to one or more of an additional interconnect structure, an electrical component, a power source, or a signal source.

11. The integrated circuit structure of claim 7 , wherein each of the first and second TFT structures comprises a transition metal dichalcogenide (TMD) material.

12. The integrated circuit structure of claim 11 , wherein each first TFT structure further comprises a first high-k gate dielectric and a first gate electrode, the first high-k gate dielectric disposed between the first gate electrode and the TMD material, and wherein each second TFT structure further comprises a second high-k gate dielectric and a second gate electrode, the second high-k gate dielectric disposed between the second gate electrode and the TMD material.

13. The integrated circuit structure of claim 7 , wherein each first TFT structure comprises a first channel structure, a first gate dielectric, and a first gate electrode, the first gate dielectric wrapped around the first channel structure, and the first gate electrode wrapped around the first gate dielectric, and wherein each second TFT structure comprises a second channel structure, a second gate dielectric, and a second gate electrode, the second gate dielectric wrapped around the second channel structure, and the second gate electrode wrapped around the second gate dielectric.

Assignees

• Intel Corp

Inventors

• Jezewski Christopher
• Agrawal Ashish
• Lin kevin l
• Sharma Abhishek
• Naylor Carl
• Alaan Urusa

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P14/3436

  being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title