Package structure with interconnection between chips and packaging method thereof

Patent metadata

Field	Value
Publication number	US-11670520-B2
Application number	US-202117523093-A
Country	US
Kind code	B2
Filing date	Nov 10, 2021
Priority date	Sep 28, 2021
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps. Hence, area of the daughter substrate unit is reduced; lengths of the interconnection paths are shortened, and qualities of communication and space utilization are enhanced.

First claim

What is claimed is:

1. A packaging method of interconnection between chips, including the following steps:
preparing a substrate having an upper surface and a lower surface; and the substrate including a daughter substrate unit having multiple through holes;
forming a first wiring layer on a first surface of the daughter substrate unit, and forming a second wiring layer on a second surface of the daughter substrate unit, and forming plated through holes in the through holes of the daughter substrate unit, and connecting the first wiring layer electrically with the second wiring layer through the plated through holes;
configuring a mother substrate interconnecting bump on the first wiring layer, wherein the mother substrate interconnecting bump is configured at a perimeter of the daughter substrate unit; and
performing a cutting procedure along the perimeter of the daughter substrate unit to expose a lateral face of the mother substrate interconnecting bump.

2. The packaging method of interconnection between chips as claimed in claim 1 , including the following step:
configuring a solder layer on a lateral face of the mother substrate interconnecting bump.

3. The packaging method of interconnection between chips as claimed in claim 2 , including the following step:
configuring a first chip on the first wiring layer of the daughter substrate unit, and configuring a second chip on the second wiring layer of the daughter substrate unit, wherein, the first chip electrically connects with the second chip through the first wiring layer, the second wiring layer and each of the plated through holes.

4. The packaging method of interconnection between chips as claimed in claim 2 , including the following steps:
performing build-up wiring layer processes on the first wiring layer and the second wiring layer to respectively configure a first build-up wiring layer structure on the first wiring layer and a second build-up wiring layer structure on the second wiring layer;
configuring a first solder mask layer and a second solder mask layer respectively on the first build-up wiring layer structure and the second build-up wiring layer structure, and the first solder mask layer exposing multiple first chip solder pads of the first build-up wiring layer structure, and the second solder mask layer exposing multiple second chip solder pads of the second build-up wiring layer structure.

5. The packaging method of interconnection between chips as claimed in claim 4 , including the following steps:
removing portions of the first solder mask layer and the first build-up wiring layer structure along the perimeter of the daughter substrate unit to expose a top face of the mother substrate interconnecting bump; wherein,
in the step of configuring a solder layer on a lateral face of the mother substrate interconnecting bump, the solder layer extends from the lateral face of the mother substrate interconnecting bump to the top face of the mother substrate interconnecting bump.

6. The packaging method of interconnection between chips as claimed in claim 1 , including the following steps:
forming a seeding layer beforehand on the upper surface and the lower surface of the substrate; and after completing the step of configuring a mother substrate interconnecting bump on the first wiring layer, the method further including:
removing portions of the seeding layer not covered by the first wiring layer and the second wiring layer.

7. The packaging method of interconnection between chips as claimed in claim 1 , wherein, the substrate includes multiple daughter substrate units, and each of the multiple daughter substrate units is arranged periodically.

8. The packaging method of interconnection between chips as claimed in claim 7 , wherein, the substrate further includes multiple cutting zones, and each of the multiple cutting zones is arranged between corresponding sides of two adjacent said daughter substrate units;
in the step of performing the cutting procedure along the perimeter of the daughter substrate unit to expose the lateral face of the mother substrate interconnecting bump, all the materials in each of the multiple cutting zones are removed to expose the lateral face of the mother substrate interconnecting bump towards the cutting zone.

9. The packaging method of interconnection between chips as claimed in claim 2 , wherein, before the step of performing the cutting procedure along the perimeter of the daughter substrate unit to expose the lateral face of the mother substrate interconnecting bump, the following steps are further included:
covering the first wiring layer and the second wiring layer respectively with a protection layer; and
after completing the step of configuring a solder layer on a lateral face of the mother substrate interconnecting bump, the following step is further included:
removing the protection layer on the first wiring layer and the second wiring layer.

10. The packaging method of interconnection between chips as claimed in claim 3 , after completing the step of configuring a solder layer on a lateral face of the mother substrate interconnecting bump, the following step is further included:
detaching the daughter substrate unit from other portions of the substrate to complete an independent daughter carrier substrate, wherein, the first chip and the second chip are configured on the daughter carrier substrate.

11. The packaging method of interconnection between chips as claimed in claim 10 , further including the following steps:
preparing a mother carrier substrate which includes multiple wiring layers, and a daughter carrier substrate accommodating slot; the daughter carrier substrate accommodating slot including a sidewall, and a lateral face contact of the multiple wiring layers protruding from the sidewall;
inserting the daughter carrier substrate mounted with the first chip and the second chip into the daughter carrier substrate accommodating slot, so that the lateral face of the mother substrate interconnecting bump faces towards the sidewall of the daughter carrier accommodating slot; and
connecting the mother substrate interconnecting bump with the lateral face contact of the mother carrier substrate through the solder layer.

12. A package structure with interconnection between chips, including:
a daughter carrier substrate including a substrate, wiring layers and a mother substrate interconnecting bump, and the daughter carrier substrate having a first surface and a second surface opposite to the first surface; the mother substrate interconnecting bump being configured on a wiring layer of the multiple wiring layers and on a perimeter of the daughter carrier substrate, and a lateral face of the mother substrate interconnecting bump being exposed towards the outside of the daughter carrier substrate.

13. The package structure with interconnection between chips as claimed in claim 12 , further including:
a solder layer configured on the lateral face of the mother substrate interconnecting bump.

14. The package structure with interconnection between chips as claimed in claim 13 , wherein,
the mother substrate interconnecting bump has a top face, and the solder layer extends from the lateral face of the mother substrate interconnecting bump to the top face of the mother substrate interconnecting bump.

15. The package structure with interconnection between chips as claimed in claim 13 , further including:
a first chip, configured on the first surface of the daughter carrier substrate, and electrically connected with a wiring layer of the first surface; and
a second chip, configured

Assignees

• Unimicron Technology Corp

Inventors

• Chen Jia Shiang
• Lan Chung-Yu
• Chen Yu-Shen

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/657 Primary

  on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers · CPC title

• H10W70/635

  Through-vias · CPC title