Determine bit error count based on signal and noise characteristics centered at an optimized read voltage

Patent metadata

Field	Value
Publication number	US-11670396-B2
Application number	US-202117551564-A
Country	US
Kind code	B2
Filing date	Dec 15, 2021
Priority date	May 7, 2020
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

A memory device to estimate a bit error count of data retrievable from a group of memory cells. For example, the memory device has a group of memory cells programmed to store a predetermined number of bits per memory cells to be read at a plurality of first voltages. The memory device determines a plurality of calibrated read voltages corresponding to the plurality of first voltages respectively, based on first signal and noise characteristics of the group of memory cells. The first signal and noise characteristics are used to compute second signal and noise characteristics of the group of memory cells for the calibrated read voltages. The second signal and noise characteristics are used in an empirical formula to compute an estimate of the bit error count of data retrievable from the group of memory cells using the calibrated read voltages.

First claim

What is claimed is:

1. A device, comprising:
memory cells;
a read circuit configured to apply voltages to the memory cells to determine states of the memory cells; and
a logic circuit coupled to the read circuit and configured to:
receive first data representative of first signal and noise characteristics of the memory cells;
determine, from the first data, a plurality of read voltages to read the memory cells at a plurality of voltage levels respectively;
compute, from the first data, second data representative of second signal and noise characteristics of the memory cells according to the plurality of read voltages; and
estimate, based on the second data, a bit error count of data retrievable using the plurality of read voltages from the memory cells.

2. The device of claim 1 , further comprising:
an integrated circuit package configured to enclose at least the memory cells, the read circuit, and the logic circuit.

3. The device of claim 1 , wherein the logic circuit is further configured to:
calculate a sum of the second signal and noise characteristics for the plurality of read voltages; and
scale the sum by a factor to estimate the bit error count.

4. The device of claim 3 , wherein the logic circuit is further configured to:
compute the factor from the sum according to a predetermined formula.

5. The device of claim 4 , wherein the predetermined formula is a linear function of the sum with predetermined coefficients.

6. The device of claim 1 , wherein to measure the first signal and noise characteristics at a voltage level among the plurality of voltage levels, the logic circuit is configured to:
determine, using the read circuit, first states of memory cells at each respective test voltage among a plurality of first test voltages that are equally spaced according to a predetermined voltage gap;
determine a bit count at the respective test voltage, the bit count corresponding to a count of a subset of the memory cells having a predetermined state when the test voltage is applied; and
compute first count differences, each of the count difference corresponding to a difference between bit counts at two the plurality of first test voltages.

7. The device of claim 6 , wherein the logic circuit is configured to determine, for the voltage level, a respective read voltage among the plurality of read voltages based on a minimum of the first count differences over the plurality of first test voltages.

8. The device of claim 7 , wherein the second signal and noise characteristics include, for the voltage level among the plurality of voltage levels, second count differences over second test voltages calculated from the first count differences over the plurality of first test voltages.

9. The device of claim 8 , wherein the second test voltages include:
an upper voltage that is one half of the predetermined voltage gap above the respective read voltage, and
a lower voltage that is one half of the predetermined voltage gap below the respective read voltage.

10. The device of claim 8 , wherein at least two of the second test voltages do not coincide with any of the first test voltages.

11. A method, comprising:
receiving first data representative of first signal and noise characteristics of memory cells in a device;
determining, from the first data, a plurality of read voltages to read the memory cells at a plurality of voltage levels respectively;
computing, from the first data, second data representative of second signal and noise characteristics of the memory cells according to the plurality of read voltages; and
estimating, based on the second data, a bit error count of data retrievable using the plurality of read voltages from the memory cells.

12. The method of claim 11 , further comprising:
calculating a sum of the second signal and noise characteristics for the plurality of read voltages; and
scaling the sum by a factor to estimate the bit error count.

13. The method of claim 12 , further comprising:
computing the factor from the sum according to a predetermined formula.

14. The method of claim 13 , wherein the predetermined formula is a linear function of the sum with predetermined coefficients.

15. The method of claim 11 , further comprising:
measuring the first signal and noise characteristics at a voltage level among the plurality of voltage levels, by:
determining, using the read circuit, first states of memory cells at each respective test voltage among a plurality of first test voltages that are equally spaced according to a predetermined voltage gap;
determining a bit count at the respective test voltage, the bit count corresponding to a count of a subset of the memory cells having a predetermined state when the test voltage is applied; and
computing first count differences, each of the count difference corresponding to a difference between bit counts at two the plurality of first test voltages.

16. The method of claim 15 , further comprising:
determining, for the voltage level, a respective read voltage among the plurality of read voltages based on a minimum of the first count differences over the plurality of first test voltages;
wherein the second signal and noise characteristics include, for the voltage level among the plurality of voltage levels, second count differences over second test voltages calculated from the first count differences over the plurality of first test voltages; and
wherein at least two of the second test voltages do not coincide with any of the first test voltages.

17. The method of claim 16 , wherein the second test voltages include:
an upper voltage that is one half of the predetermined voltage gap above the respective read voltage, and
a lower voltage that is one half of the predetermined voltage gap below the respective read voltage.

18. An apparatus, comprising:
a processing device configured to transmit a command having an address; and
a memory device having:
memory cells formed on an integrated circuit die;
a first circuit operable to apply voltages to the memory cells and determine states of the memory cells being applied to the voltages; and
a second circuit coupled to the first circuit and configured to, in response to the address in the command identifying the memory cells:
receive, from the first circuit, first data representative of first signal and noise characteristics of the memory cells;
determine, from the first data, a plurality of read voltages to read the memory cells at a plurality of voltage levels respectively;
compute, from the first data, second data representative of second signal and noise characteristics of the memory cells according to the plurality of read voltages; and

estimate, based on the second data, a bit error count of data retrievable using the plurality of read voltages from the memory cells.

19. The apparatus of claim 18 , wherein the first signal and noise characteristics are representative of, for each voltage level among the plurality of voltage levels evenly separated by a predetermined voltage gap, first count differences over a first plurality of test voltages;
wherein each count difference among the first count differences being a difference between:
a first count of a first subset of the memory cells having a predetermined state when a first test voltage among the first plurality of test voltages is applied to the memory cells; and
a second count of a second subset of the memory cells having the predetermined state when a second test voltage among the first plurality of test voltages

Assignees

• Micron Technology Inc

Inventors

• Khayat Patrick Robert
• Parthasarathy Sivagnanam
• Fitzpatrick James

Classifications

• G11C29/4401

  for self repair · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/50004 Primary

  of threshold voltage · CPC title