Apparatuses and methods for refreshing memory of a semiconductor device

Patent metadata

Field	Value
Publication number	US-10910034-B2
Application number	US-201916538603-A
Country	US
Kind code	B2
Filing date	Aug 12, 2019
Priority date	Jan 19, 2018
Publication date	Feb 2, 2021
Grant date	Feb 2, 2021

Abstract

Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.

First claim

What is claimed is:

1. A method, comprising:
producing, responsive to a first refresh command, a plurality of first refresh addresses by combining at least a portion of a refresh address with a respective count provided by a count circuit to provide a respective one of the plurality of first refresh addresses;
detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address; and
refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.

2. The method of claim 1 , further comprising:
producing, responsive to the second refresh command, a plurality of second refresh addresses different from the plurality of first refresh addresses; and
detecting, responsive to the plurality of second refresh addresses, that the plurality of second refresh addresses include a second defective address and a second non-defective address.

3. The method of claim 2 , further comprising:
refreshing, responsive to a third refresh command following the second refresh command, the non-defective second address without refreshing the second defective address.

4. The method of claim 1 , wherein detecting that the plurality of first refresh addresses include a first defective address and a first non-defective address is performed one by one.

5. The method of claim 4 , wherein detecting that the plurality of first refresh addresses include a first defective address and a first non-defective address is performed by comparing the plurality of first refresh addresses to a plurality of defective address stored in a plurality of fuse circuits.

6. The method of claim 3 , wherein each of the first refresh command, the second refresh command and the third refresh command is one of an auto refresh command and a self-refresh command.

Assignees

• Micron Technology Inc

Inventors

• Morohashi Masaru

Classifications

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C29/76

  using address translation or modifications · CPC title

• G11C11/4097 Primary

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/406

  Management or control of the refreshing or charge-regeneration cycles · CPC title