Apparatus and methods to provide power management for memory devices

Patent metadata

Field	Value
Publication number	US-11670343-B2
Application number	US-202117464039-A
Country	US
Kind code	B2
Filing date	Sep 1, 2021
Priority date	Sep 6, 2012
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

First claim

The invention claimed is:

1. A method, comprising:
operating a memory device in a low-latency mode, the memory device to operate in the low-latency mode and a low-power mode different than the low-latency mode;
determining a bias level of a word line of the memory device based at least in part on the memory device operating in the low-latency mode; and
accessing a memory cell of the memory device based at least in part on the bias level.

2. The method of claim 1 , further comprising:
receiving an indication from a processor, wherein determining the bias level of the word line of the memory device is based at least in part on receiving the indication.

3. The method of claim 2 , wherein the indication comprises mode information associated with the low-latency mode or the low-power mode.

4. The method of claim 1 , further comprising:
determining an information transfer parameter associated with the memory cell of the memory device, wherein operating in the low-latency mode is based at least in part on the information transfer parameter.

5. The method of claim 1 , further comprising:
determining whether a predicted number of write operations performed by the memory device satisfies a threshold, wherein operating in the low-latency mode is based at least in part on the predicted number of write operations failing to satisfy the threshold.

6. The method of claim 1 , further comprising:
initiating operation of the memory device in the low-power mode based at least in part on an amount of power consumed by the memory device, an amount of latency in one or more access operations, a number of memory cells in the memory device, or a combination thereof.

7. The method of claim 1 , wherein:
the low-power mode is a read-only mode; and
the low-latency mode is a read/write mode.

8. The method of claim 1 , further comprising:
identifying data to be written to the memory cell of the memory device;
determining that the low-power mode that the memory device is operating in is a read-only mode;
initiating operation of memory device in the low-latency mode; and
writing the identified data to the memory cell while the memory device is operating in the low-latency mode.

9. The method of claim 1 , further comprising:
determining a second bias level of a deselected word line of the memory device based at least in part on operating the memory device in the low-latency mode, wherein accessing the memory cell is based at least in part on the second bias level of the deselected word line.

10. The method of claim 1 , further comprising:
enabling an overlay window based at least in part on determining the bias level, wherein the overlay window is for controlling the bias level of the word line associated with the memory cell.

11. The method of claim 10 , further comprising:
writing information to a register of a command interface, wherein enabling the overlay window is based at least in part writing the information to the register.

12. The method of claim 1 , further comprising:
determining that the low-latency mode is a default mode of operation, wherein operating the memory device in the low-latency mode is based at least in part on determining that the low-latency mode is the default mode of operation.

13. A method, comprising:
operating, by a memory device, in a low-latency mode using a first bias level of a word line of the memory device;
determining an information transfer parameter associated with a memory cell of the memory device; and
initiating operation of the memory device in a low-power mode different from the low-latency mode based at least in part on determining the information transfer parameter.

14. The method of claim 13 , further comprising:
determining a second bias level of the word line of the memory device based at least in part on operating in the low-power mode, the second bias level being different than the first bias level.

15. The method of claim 14 , further comprising:
accessing the memory cell of the memory device based at least in part on the second bias level associated with the low-power mode.

16. The method of claim 13 , wherein determining the information transfer parameter further comprises:
determining that a predicted number of write operations of the memory device fails to satisfy a threshold, wherein initiating the low-power mode is based at least in part on the predicted number of write operations failing to satisfy the threshold.

17. A method, comprising:
operating, by a memory device, in a low-latency mode;
determining a first bias level of a word line of the memory device based at least in part on operating in the low-latency mode, the first bias level being greater than a second bias level associated with a low-power mode of the memory device; and
determining a logic state stored on a memory cell of the memory device using the first bias level.

18. The method of claim 17 , further comprising:
applying the first bias level to the word line during a read operation, wherein determining the logic state is based at least in part on applying the first bias level.

19. The method of claim 17 , further comprising:
enabling an overlay window based at least in part on operating in the low-latency mode, wherein the overlay window is for controlling a bias level of the word line associated with the memory cell during an access operation.

20. The method of claim 17 , further comprising:
activating a linear down regulator based at least in part on operating in the low-latency mode, wherein the linear down regulator is for generating the first bias level by reducing a voltage level associated with the second bias level.

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Barkley Gerald
• Hendrickson Nicholas

Classifications

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title