III-N metal-insulator-semiconductor field effect transistors with multiple gate dielectric materials

Patent metadata

Field	Value
Publication number	US-11664417-B2
Application number	US-201816130911-A
Country	US
Kind code	B2
Filing date	Sep 13, 2018
Priority date	Sep 13, 2018
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

Integrated circuits with III-N metal-insulator-semiconductor field effect transistor (MISFET) structures that employ one or more gate dielectric materials that differ across the MISFETs. Gate dielectric materials may be selected to modulate dielectric breakdown strength and/or threshold voltage between transistors. Threshold voltage may be modulated between two MISFET structures that may be substantially the same but for the gate dielectric. Control of the gate dielectric material may render some MISFETs to be operable in depletion mode while other MISFETs are operable in enhancement mode. Gate dielectric materials may be varied by incorporating multiple dielectric materials in some MISFETs of an IC while other MISFETs of the IC may include only a single dielectric material. Combinations of gate dielectric material layers may be selected to provide a menu of low voltage, high voltage, enhancement and depletion mode MISFETs within an IC.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a first transistor, comprising:
a first source and a first drain coupled through a first group III-nitride (III-N) material;
a first gate electrode between the first source and the first drain; and

a first gate dielectric material between the first gate electrode and the first III-N material,
wherein the first gate dielectric material is in contact with the first gate electrode and comprises a metal and oxygen, wherein the first gate dielectric material is in contact with a second III-N material that is in contact with the first III-N material, and wherein the second III-N material comprises more Al than the first III-N material; and

a second transistor, comprising:
a second source and a second drain coupled through the first III-N material;
a second gate electrode between the second source and the second drain; and
the first gate dielectric material and a second gate dielectric material between the second gate electrode and the second III-N material, wherein the second gate dielectric material is in contact with the second gate electrode and comprises silicon, and wherein the first gate dielectric material is in contact with the second III-N material and the second III-N material is in contact with the first III-N material.

2. The IC of claim 1 , wherein the second gate dielectric material comprises oxygen.

3. The IC of claim 2 , wherein the gate second dielectric material is in contact with the first gate dielectric material.

4. The IC of claim 3 , wherein the first gate electrode and the second gate electrode have substantially the same composition.

5. The IC of claim 4 , wherein the first transistor is an enhancement mode transistor and the second transistor is a depletion mode transistor.

6. The IC of claim 1 , wherein
the first transistor has a lower gate-drain breakdown voltage than the second transistor.

7. The IC of claim 1 , wherein the second gate dielectric material comprises nitrogen.

8. The IC of claim 1 , wherein the metal is at least one of Hf or Al.

9. The IC of claim 1 , further comprising a third transistor, the third transistor comprising:
a third source and a third drain coupled through the first III-N material;
a third gate electrode between the third source and the third drain; and
a third gate dielectric material between the third gate electrode and the second III-N material,
wherein the third gate dielectric material is in contact with the third gate electrode and has a different composition than the first or second gate dielectric materials.

10. The IC of claim 9 , wherein the third transistor further comprises at least one of the first and second gate dielectric materials in addition to the third gate dielectric material.

11. The IC of claim 10 , wherein the third transistor further comprises both of the first and second gate dielectric materials in addition to the third gate dielectric material, and wherein the third gate dielectric material has more nitrogen than the second gate dielectric material.

12. The IC of claim 11 , wherein:
the first transistor is an enhancement mode transistor;
the second transistor and the third transistor are depletion mode transistors; and
the third transistor has a higher gate-drain breakdown voltage than the first transistor.

13. The IC of claim 1 , wherein:
the first III-N material comprises Ga and N; and
the second III-N material is absent from between the first III-N material and the first gate dielectric material for both the first and second transistors.

Assignees

• Intel Corp

Inventors

• Hafez Walid
• Then Han Wui
• Dasgupta Sansaptak
• Radosavljevic Marko
• Fischer Paul

Classifications

• H10D84/84 Primary

  Combinations of enhancement-mode IGFETs and depletion-mode IGFETs · CPC title

• H10D84/0163

  the components including enhancement-mode IGFETs and depletion-mode IGFETs · CPC title

• H10D84/014

  the gate conductors having different materials or different implants · CPC title

• H10D84/83135

  the IGFETs characterised by having different gate conductor materials or different gate conductor implants · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title