Package structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11664339-B2
Application number	US-202016854730-A
Country	US
Kind code	B2
Filing date	Apr 21, 2020
Priority date	Apr 21, 2020
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A package structure and a manufacturing method are provided. The package structure includes a first circuit layer, a first dielectric layer, an electrical device and a first conductive structure. The first circuit layer includes a first alignment portion. The first dielectric layer covers the first circuit layer. The electrical device is disposed on the first dielectric layer, and includes an electrical contact aligning with the first alignment portion. The first conductive structure extends through the first alignment portion, and electrically connects the electrical contact and the first alignment portion.

First claim

What is claimed is:

1. A package structure, comprising:
a first circuit layer including a first alignment portion;
a first dielectric layer covering the first circuit layer;
an electrical device disposed on the first dielectric layer, and including an electrical contact aligning with the first alignment portion;
a first conductive structure extending through the first alignment portion, and electrically connecting the electrical contact and the first alignment portion;
a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer defines an opening exposing a portion of a bottom surface of the first conductive structure, wherein in a cross-sectional view, a width of the opening of the second dielectric layer is less than a width of the bottom surface of the first conductive structure; and
a conductive via disposed in the opening of the second dielectric layer, wherein in a cross-sectional view, a width of the conductive via reduces toward the first conductive structure.

2. The package structure of claim 1 , wherein the first alignment portion and the first conductive structure are not formed concurrently.

3. The package structure of claim 1 , wherein a lateral side surface of the first conductive structure is physically connected to the first alignment portion of the first circuit layer directly.

4. The package structure of claim 1 , wherein a top surface of the first conductive structure is physically connected to the electrical contact of the electrical device directly.

5. The package structure of claim 1 , further comprising:
an encapsulant covering the electrical device and the first dielectric layer, wherein a lateral side surface of the encapsulant is substantially coplanar with a lateral side surface of the first dielectric layer.

6. The package structure of claim 1 , further comprising a solder disposed on the first conductive structure, wherein a width of the solder is greater than a width of the first conductive structure.

7. The package structure of claim 1 , wherein a thickness of the first conductive structure is greater than a thickness of the first circuit layer.

8. The package structure of claim 7 , wherein the first dielectric layer contacts a lateral surface of the first circuit layer.

9. The package structure of claim 1 , wherein first alignment portion contacts a portion of a lateral surface of the first conductive structure.

10. The package structure of claim 9 , wherein first alignment portion is around the first conductive structure.

11. The package structure of claim 1 , wherein a diameter of an opening of the first alignment portion is less than a width of the electrical contact.

12. The package structure of claim 11 , wherein a width of the first conductive structure is less than a width of the electrical contact.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title