Memory system performance enhancements using measured signal and noise characteristics of memory cells

Patent metadata

Field	Value
Publication number	US-11662905-B2
Application number	US-202117552179-A
Country	US
Kind code	B2
Filing date	Dec 15, 2021
Priority date	Dec 13, 2019
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A memory sub-system configured to improve performance using signal and noise characteristics of memory cells measured during the execution of a command in a memory component. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing the command in the memory component. A processing device separate from the memory component transmits the command to the memory component, and receives and processes the signal and noise characteristics to identify an attribute about the memory component. Subsequently, an operation related to data stored in the memory component can be performed based on the attribute.

First claim

What is claimed is:

1. A device, comprising:
at least one group of memory cells;
a read circuit configured to apply read voltages on the memory cells to determine states of the memory cells; and
a logic circuit configured to, in response to a read command:
instruct the read circuit to apply first voltages on the memory cells;
determine, for the first voltages respectively, counts of memory cells in subsets of the group of memory cells, wherein each count of the counts is a number of memory cells, among the group of memory cells being applied a respective voltage among the first voltages, having a predetermined state;
compute a read voltage based on the counts;
instruct the read circuit to read the group of memory cells using the read voltage;
determine first data stored in the group of memory cells based on states of the group of memory cells under the read voltage; and
provide a response to the read command to include second data representative of differences between the counts at adjacent ones of the first voltages.

2. The device of claim 1 , further comprising:
an integrated circuit package configured to enclose at least the group of memory cells, the read circuit, and the logic circuit;
wherein the response to the read command further includes the first data determined using the read voltage.

3. The device of claim 2 , wherein the read circuit and the group of memory cells are formed as part of an integrated circuit die.

4. The device of claim 3 , wherein the response to the read command is configured to identify the counts at the first voltages.

5. The device of claim 1 , wherein the response to the read command is further configured to include third data representative of the read voltage used to determine the first data.

6. A method, comprising:
transmitting, by a processing device in a memory sub-system, a read command to a memory device of the memory sub-system, the read command identifying a group of memory cells within the memory device, wherein the memory device is configured to determine responses of the group of memory cells to a plurality of operating parameters;
receiving, in the processing device from the memory device, a response to the read command, the response including data representative of statistics about the group of memory cells responding to the plurality of operating parameters; and
determining, by the processing device from the statistics provided in the response at the plurality of operating parameters, an attribute of the group of memory cells.

7. The method of claim 6 , further comprising:
performing, based on the attribute, an operation related to data stored in the memory device.

8. The method of claim 7 , wherein the attribute is configured to indicate whether there is a program failure in first data retrieved from the group of memory cells and provided in the response to the read command; and in response to the attribute indicating a program failure, the operation includes skipping decoding first data, or skipping handling errors in the first data, or any combination thereof.

9. The method of claim 7 , wherein the attribute is representative of a voltage optimized to read the group of memory cells, or an amount of damage in the memory device as a result of program/erase cycles.

10. The method of claim 6 , wherein the plurality of operating parameters include a plurality of test voltages to read the group of memory cells; and the statistics include data representative of a plurality of differences, each of the differences corresponding to a difference between:
a first count of a first portion of the group of memory cells having a predetermined state when a first test voltage among the plurality of test voltages is applied to the group of memory cells; and
a second count of a second portion of the group of memory cells having the predetermined state when a second test voltage among the plurality of test voltages is applied to the group of memory cells.

11. The method of claim 6 , wherein the attribute is computed based at least in part on second data relevant to charge loss, read disturb, cross-temperature effect, data retention, or program/erase, or any combination thereof.

12. The method of claim 6 , further comprising:
generating a predictive model using the statistics provided in the response to the read command, wherein the attribute is computed based on the predictive model.

13. The method of claim 6 , further comprising:
tracking shifting of optimized read voltage as a function of operating temperature to determine the attribute configured to be representative of margin loss from cross-temperature effect.

14. A non-transitory computer storage medium storing instructions which, when executed by a computing system, cause the computing system to perform a method, the method comprising:
transmitting, by a processing device in the computing system, a read command to a memory device in the computing system, the read command identifying a group of memory cells within the memory device, wherein the memory device is configured to determine responses of the group of memory cells to a plurality of operating parameters;
receiving, in the processing device from the memory device, a response to the read command, the response including data representative of statistics about the group of memory cells responding to the plurality of operating parameters; and
determining, by the processing device from the statistics provided in the response at the plurality of operating parameters, an attribute of the group of memory cells.

15. The non-transitory computer storage medium of claim 14 , wherein the method further comprises:
performing, based on the attribute, an operation related to data stored in the memory device;
wherein the attribute is configured to indicate whether there is a program failure in first data retrieved from the group of memory cells and provided in the response to the read command; and in response to the attribute indicating a program failure, the operation includes skipping decoding first data, or skipping handling errors in the first data, or any combination thereof.

16. The non-transitory computer storage medium of claim 14 , wherein the attribute is representative of:
a voltage optimized to read the group of memory cells; or
an amount of damage in the memory device as a result of program/erase cycles.

17. The non-transitory computer storage medium of claim 14 , wherein the plurality of operating parameters include a plurality of test voltages to read the group of memory cells; and the statistics include data representative of a plurality of differences, each of the differences corresponding to a difference between:
a first count of a first portion of the group of memory cells having a predetermined state when a first test voltage among the plurality of test voltages is applied to the group of memory cells; and
a second count of a second portion of the group of memory cells having the predetermined state when a second test voltage among the plurality of test voltages is applied to the group of memory cells.

18. The non-transitory computer storage medium of claim 14 , wherein the attribute is computed based at least in part on second data relevant to charge loss, read disturb, cross-temperature effect, data retention, or program/erase, or any combination thereof.

19. The non-transitory computer storage medium of claim 14 , wherein the method further comprises:
generating a predictive model using the statistics provided in the response to the read command, w

Assignees

• Micron Technology Inc

Inventors

• Fitzpatrick James
• Parthasarathy Sivagnanam
• Khayat Patrick Robert
• Alhussien Abdelhakim S
• Moschiano Violante

Classifications

• G06F3/0673

  Single storage device · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title