Memory system performance enhancements using measured signal and noise characteristics of memory cells

Patent metadata

Field	Value
Publication number	US-11237726-B2
Application number	US-201916714463-A
Country	US
Kind code	B2
Filing date	Dec 13, 2019
Priority date	Dec 13, 2019
Publication date	Feb 1, 2022
Grant date	Feb 1, 2022

Abstract

A memory sub-system configured to improve performance using signal and noise characteristics of memory cells measured during the execution of a command in a memory component. For example, the memory component is enclosed in an integrated circuit and has a calibration circuit. The signal and noise characteristics are measured by the calibration circuit as a byproduct of executing the command in the memory component. A processing device separate from the memory component transmits the command to the memory component, and receives and processes the signal and noise characteristics to identify an attribute about the memory component. Subsequently, an operation related to data stored in the memory component can be performed based on the attribute.

First claim

What is claimed is:

1. A memory sub-system, comprising:
a processing device; and
at least one memory component, the memory component being enclosed in an integrated circuit package, the memory component having:
a group of memory cells formed on an integrated circuit die; and
a calibration circuit;

wherein the processing device is configured to transmit a command to the memory component to retrieve data from an address;
wherein in response to the command and during execution of the command, the calibration circuit is configured to measure signal and noise characteristics of the group of memory cells;
wherein the memory component is configured to, in response to the command:
retrieve the data using a read voltage calibrated using the signal and noise characteristics; and
provide, as a response to the command, the data and the signal and noise characteristics to the processing device, wherein the signal and noise characteristics include measurements of a quantity at a plurality of voltages in vicinity of the read voltage; and

wherein the processing device is configured to process the signal and noise characteristics having the measurements of the quantity at the plurality of voltages to identify an attribute about the memory component and perform an operation related to data stored in the memory component based on the attribute.

2. The memory sub-system of claim 1 , wherein the calibration circuit is formed at least in part on the integrated circuit die.

3. The memory sub-system of claim 1 , wherein the signal and noise characteristics include a count of memory cells in the group having a predetermined state when a read voltage is applied on the group of memory cells.

4. The memory sub-system of claim 1 , wherein the signal and noise characteristics include a difference between:
a first count of memory cells in the group having a predetermined state when a first read voltage is applied on the group of memory cells; and
a second count of memory cells in the group having the predetermined state when a second read voltage is applied on the group of memory cells.

5. The memory sub-system of claim 1 , wherein the signal and noise characteristics include statistic data of memory cells at varying operating parameters.

6. The memory sub-system of claim 5 , wherein the varying operating parameters includes different voltages applied to read memory cells in the group.

7. The memory sub-system of claim 1 , wherein the memory component is configured to further provide a first optimized read voltage calculated by the calibration circuit of the memory component from the signal and noise characteristics; and the attribute includes a second optimized read voltage calculated by the processing device using at least the signal and noise characteristics.

8. The memory sub-system of claim 7 , wherein the first optimized read voltage is calculated using a first method; and the second optimized read voltage is calculated using a second method.

9. The memory sub-system of claim 8 , wherein the second optimized read voltage is calculated based on information not available in the memory component during the execution of the command.

10. The memory sub-system of claim 9 , wherein the information not available in the memory component during the execution of the command includes further signal and noise characteristics generated by the calibration circuit during execution of one or more prior commands.

11. The memory sub-system of claim 9 , wherein the information not available in the memory component during the execution of the command includes data relevant to charge loss, read disturb, cross-temperature effect, data retention, or program/erase, or any combination thereof.

12. The memory sub-system of claim 1 , wherein the attribute includes a predictive model generated based on the signal and noise characteristics.

13. A method, comprising:
transmitting, by a processing device in a memory sub-system, a command to a memory component of the memory sub-system to retrieve data from an address, the memory component being enclosed in an integrated circuit package and configured to, in response to the command and during execution of the command, measure signal and noise characteristics of a group of memory cells formed on an integrated circuit die using a calibration circuit;
receiving, in the processing device from the memory component, the signal and noise characteristics measured by the calibration circuit during the execution of the command, the signal and noise characteristics including a plurality of measurements of a quantity at a plurality of voltages;
processing, by the processing device of the memory sub-system, the signal and noise characteristics having the plurality of measurements of the quantity at the plurality of voltages;
identifying, by the processing device of the memory sub-system, an attribute about the memory component based on the processing of the signal and noise characteristics; and
performing, an operation related to data stored in the memory component based on the attribute.

14. The method of claim 13 , wherein the attribute includes a determination of program failure in the data retrieved by the memory component from the address in response to the command; and the operation includes skipping decoding the data, or skipping recovering from errors in the data.

15. The method of claim 14 , wherein the attribute includes a predictive model of an optimized read voltage as a function of one or more factors.

16. The method of claim 15 , wherein the signal and noise characteristics include statistics of memory cells in the group operated at different levels of an operating parameter.

17. A non-transitory computer storage medium storing instructions which, when executed by a computing system, cause the computing system to perform a method, the method comprising:
transmitting, by a processing device in a memory sub-system, a command to a memory component of the memory sub-system, the command instructing the memory component to retrieve data from an address, wherein the memory component is enclosed in an integrated circuit package and is configured to, in response to the command and during execution of the command, measure signal and noise characteristics of a group of memory cells formed on an integrated circuit die using a calibration circuit;
receiving, in the processing device from the memory component, the signal and noise characteristics measured by the calibration circuit during the execution of the command, the signal and noise characteristics including a plurality of measurements of a quantity at a plurality of voltages;
processing, by the processing device of the memory sub-system, the signal and noise characteristics having the plurality of measurements of the quantity at the plurality of voltages;
identifying, by the processing device of the memory sub-system, an attribute about the memory component based the processing of the signal and noise characteristics; and
performing, an operation related to data stored in the memory component based on the attribute.

18. The non-transitory computer storage medium of claim 17 , wherein the attribute includes a predictive model generated based on the signal and noise characteristics and at least one factor, including cross-temperature effect, read disturb, program/erase, or data retention, or any combination thereof.

19. The non-transitory computer storage medium of claim 17 , wherein the attribute identifies an amount of damage the memory component has as a result of program/erase c

Assignees

• Micron Technology Inc

Inventors

• Fitzpatrick James
• Parthasarathy Sivagnanam
• Khayat Patrick Robert
• Alhussien Abdelhakim S
• Moschiano Violante

Classifications

• G11C29/028 Primary

  with adaption or trimming of parameters · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title