Semiconductor device package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11658102-B2
Application number	US-202016749635-A
Country	US
Kind code	B2
Filing date	Jan 22, 2020
Priority date	Jan 22, 2020
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than −20 dB.

First claim

What is claimed is:

1. A semiconductor device package, comprising:
a carrier;
an electronic component disposed on the carrier; and
a connector disposed on the carrier and electrically connected to the electronic component through the carrier, the connector having a first group of pins, a second group of pins and a group of common ground pins disposed between the first group of pins and the second group of pins to separate the first group of pins and the second group of pins,
wherein the connector and the electronic component are non-overlapping in a direction substantially perpendicular to a surface of the carrier, and
wherein a top surface of the connector is higher than a top surface of the electronic component.

2. The semiconductor device package of claim 1 , further comprising a conductive via, wherein the conductive via is configured to be a compartment shielding to provide electromagnetic interference (EMI) shielding between the electronic component and the connector.

3. The semiconductor device package of claim 2 , wherein the conductive via, the electronic component, and the connector are non-overlapping in a direction substantially perpendicular to a surface of the carrier.

4. The semiconductor device package of claim 3 , further comprising a package body covering the electronic component and the connector, wherein the conductive via penetrates the package body.

5. The semiconductor device package of claim 4 , wherein a height of the conductive via is substantially the same as a thickness of the package body.

6. The semiconductor device package of claim 1 , further comprising a shielding layer disposed on the connector, the shielding layer including a first opening to expose the first group of pins and a second opening to expose the second group of pins.

7. The semiconductor device package of claim 1 , further comprising:
a first package body encapsulating the connector to constitute a connector module disposed on the carrier; and
a second package body encapsulating the connector module and the electronic component.

8. The semiconductor device package of claim 1 , wherein the group of common ground pins is closer to the electronic component than the first group of pins and the second group of pins.

9. The semiconductor device package of claim 8 , wherein the group of common ground pins separates the electronic component, the first group of pins, and the second group of pins from each other.

10. A semiconductor device package, comprising:
a carrier;
an electronic component disposed on the carrier;
a connector disposed on the carrier and electrically connected to the electronic component through the carrier, the connector having a first group of pins, a second group of pins and a group of common ground pins disposed between the first group of pins and the second group of pins to separate the first group of pins and the second group of pins;
a first package body encapsulating the connector to constitute a connector module disposed on the carrier; and
a second package body encapsulating the connector module and the electronic component,
wherein a portion of the second package body is disposed between a bottom surface of the connector module and a top surface of the carrier.

11. The semiconductor device package of claim 7 , further comprising a shielding layer in contact with a top surface and a lateral surface of the second package body, wherein the shielding layer is in contact with a ground pin of the group of common ground pins exposed from the first package body.

12. The semiconductor device package of claim 6 , wherein the first opening of the shielding layer is adapted to accommodate an external device for being electrically connected to the connector.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yu Yuanhao
• Chen cheng yuan
• Chen Chun Chen
• Li Jiming
• Tu Chien-Wen

Classifications

• H10W44/203

  Electrical connections · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W42/273

  the arrangements being between laterally adjacent chips, e.g. walls between chips · CPC title

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title