Interconnect structure with dielectric cap layer and etch stop layer stack

Patent metadata

Field	Value
Publication number	US-11658064-B2
Application number	US-202117210015-A
Country	US
Kind code	B2
Filing date	Mar 23, 2021
Priority date	Sep 29, 2020
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a metal cap layer over an upper surface of the first conductive feature distal from the substrate; selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first conductive feature in a first dielectric layer disposed over a substrate;
forming a metal cap layer over an upper surface of the first conductive feature distal from the substrate;
selectively forming a dielectric cap layer over an upper surface of the first dielectric layer and laterally adjacent to the metal cap layer, wherein the metal cap layer is exposed by the dielectric cap layer; and
forming an etch stop layer stack over the metal cap layer and the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers.

2. The method of claim 1 , further comprising:
forming a second dielectric layer over the etch stop layer stack; and
forming a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the etch stop layer stack and is electrically coupled to the metal cap layer.

3. The method of claim 1 , wherein forming the metal cap layer comprises selectively forming an electrically conductive material over the upper surface of the first conductive feature.

4. The method of claim 1 , wherein the dielectric cap layer is formed of a nitride-containing dielectric material.

5. The method of claim 4 , wherein the nitride-containing dielectric material is silicon nitride, silicon oxynitride, or silicon carbonitride.

6. The method of claim 4 , wherein a thickness of the dielectric cap layer is between about 10 angstroms and about 50 angstroms.

7. The method of claim 4 , wherein selectively forming the dielectric cap layer comprises selectively depositing the nitride-containing dielectric material over the upper surface of the first dielectric layer using a plasma-enhanced chemical vapor deposition (PECVD) process.

8. The method of claim 7 , wherein the PECVD process is performed using a precursor comprising N 2 , NH 3 , NO, or N 2 O.

9. The method of claim 4 , wherein selectively forming the dielectric cap layer comprises converting an upper layer of the first dielectric layer into the dielectric cap layer by performing an ion implantation process.

10. The method of claim 9 , wherein the ion implantation process is performed using a gas source comprising NH 3 or N 2 O.

11. The method of claim 4 , wherein forming the etch stop layer stack comprises:
forming a layer of aluminum nitride over the metal cap layer and the dielectric cap layer;
forming a layer of oxygen-doped silicon carbide over the layer of aluminum nitride; and
forming a layer of aluminum oxide over the layer of oxygen-doped silicon carbide.

12. The method of claim 11 , wherein forming the etch stop layer stack further comprises forming another layer of aluminum oxide between the layer of aluminum nitride and the layer of oxygen-doped silicon carbide.

13. A method of forming a semiconductor device, the method comprising:
forming first conductive features in a first dielectric layer disposed over a substrate, wherein first surfaces of the first conductive features distal from the substrate are level with a first surface of the first dielectric layer;
selectively forming a metal cap layer on the first surfaces of the first conductive features;
selectively forming a dielectric cap layer on the first surface of the first dielectric layer, wherein the dielectric cap layer is laterally adjacent to the metal cap layer, wherein the dielectric cap layer is formed of a nitride-containing dielectric material;
forming a plurality of etch stop layers successively on the metal cap layer and on the dielectric cap layer;
forming a second dielectric layer on the plurality of etch stop layers; and
forming second conductive features in the second dielectric layer, wherein the second conductive features extend through the plurality of etch stop layers and are electrically coupled to respective ones of the first conductive features.

14. The method of claim 13 , wherein selectively forming the dielectric cap layer comprises depositing the nitride-containing dielectric material on the first surface of the first dielectric layer while keeping an upper surface of the metal cap layer distal from the substrate free of the nitride-containing dielectric material, wherein the nitride-containing dielectric material extends continuously between adjacent ones of the first conductive features.

15. The method of claim 13 , wherein selectively forming the dielectric cap layer comprises converting an upper portion of the first dielectric layer proximate to the first surface of the first dielectric layer into the dielectric cap layer by an ion implantation process.

16. The method of claim 13 , wherein forming the plurality of etch stop layers comprises:
forming a first etch stop layer comprising aluminum nitride over the metal cap layer and the dielectric cap layer;
forming a second etch stop layer comprising oxygen-doped silicon carbide over the first etch stop layer; and
forming a third etch stop layer comprising aluminum oxide over the second etch stop layer.

17. The method of claim 13 , wherein forming the second conductive features comprises:
forming conductive lines in the second dielectric layer; and
forming vias underlying the conductive lines, wherein upper portions of the vias are in the second dielectric layer, and lower portions of the vias extend through the plurality of etch stop layers and are electrically coupled to the first conductive features.

18. A method of forming a semiconductor device, the method comprising:
forming a first conductive feature in a first dielectric layer, wherein the first dielectric layer is formed over a substrate;
forming a metal cap layer on the first conductive feature;
forming a dielectric cap layer on an upper surface of the first dielectric layer distal from the substrate, wherein the dielectric cap layer is formed to be laterally adjacent to the metal cap layer, wherein the dielectric cap layer is formed of a nitride-containing dielectric material, wherein an upper surface of the metal cap layer distal from the substrate is free of the dielectric cap layer;
forming an etch stop layer stack on the metal cap layer and on the dielectric cap layer, wherein the etch stop layer stack comprises a plurality of etch stop layers;
forming a second dielectric layer on the etch stop layer stack; and
forming a second conductive feature in the second dielectric layer, wherein the second conductive feature extends through the etch stop layer stack and is electrically coupled to the first conductive feature.

19. The method of claim 18 , wherein forming the etch stop layer stack comprises:
forming a first etch stop layer comprising aluminum nitride over the metal cap layer and the dielectric cap layer;
forming a second etch stop layer comprising oxygen-doped silicon carbide over the first etch stop layer; and
forming a third etch layer comprising aluminum oxide over the second etch stop layer.

20. The method of claim 18 , wherein forming the second conductive feature comprises:
forming a metal line in the second dielectric layer, wherein a lower surface of the meta line facing the substrate is spaced apart from the etch stop layer stack; and
forming a via underlying and connected to the metal line, wherein the via extends through the etch stop layer stack and contacts the metal cap layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chao-Chun
• Wang Jen Hung

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/075 Primary

  of multilayered thin functional dielectric layers · CPC title

• H10W20/057

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title