Etch stop layer for semiconductor devices

Patent metadata

Field	Value
Publication number	US-11322396-B2
Application number	US-201816043343-A
Country	US
Kind code	B2
Filing date	Jul 24, 2018
Priority date	Jun 29, 2016
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

First claim

What is claimed is:

1. A method comprising:
receiving a substrate having a source/drain feature disposed thereon, the source/drain feature including a topmost surface facing away from the substrate, wherein the receiving of the substrate having the source/drain feature disposed thereon includes the substrate having a fin structure and the source/drain feature at least partially embedded in the fin structure;
forming an etch stop layer on the substrate and the source/drain feature, wherein the forming of the etch stop layer includes:
forming a first layer having a first composition on the substrate and the source/drain feature such that the first layer physically contacts the topmost surface of the source/drain feature; and
forming a second layer having a second composition that is different from the first composition on the first layer;

etching a portion of the etch stop layer to define a trench within the etch stop layer, wherein a first portion of the topmost surface of the source/drain feature remains covered by a portion of the first layer while a second portion of the topmost surface of the source/drain feature is exposed after the etching of the portion of the etch stop layer to define the trench; and
forming a conductive feature within the trench that extends through the etch stop layer.

2. The method of claim 1 , wherein the first layer includes a semiconductor-containing dielectric.

3. The method of claim 2 , wherein the second layer includes a metal-containing dielectric.

4. The method of claim 1 , wherein the substrate has a gate structure disposed on the substrate, and the forming of the etch stop layer forms the etch stop layer on the gate structure.

5. The method of claim 4 , wherein the forming of the etch stop layer forms the etch stop layer on a top surface of the gate structure and on a side surface of the gate structure.

6. The method of claim 1 , wherein the first layer physically contacts the second layer.

7. The method of claim 1 , wherein the first layer includes carbon and nitrogen.

8. The method of claim 1 , wherein the first layer includes silicon and the second layer includes a metal nitride.

9. A method comprising:
receiving a substrate;
forming a semiconductor fin structure on the substrate, the semiconductor fin structure having a top surface facing away from the substrate;
forming a source/drain feature disposed on and interfacing with the top surface of the semiconductor fin structure;
forming an etch stop layer on the substrate that includes a semiconductor-containing dielectric layer and a metal-containing dielectric layer disposed on the semiconductor-containing dielectric layer, wherein the semiconductor-containing dielectric layer includes silicon, nitrogen and carbon, wherein the forming of the etch stop layer on the substrate includes forming the etch stop layer on the source/drain feature such that the semiconductor-containing dielectric layer interfaces with a side surface and a top surface of the source/drain feature, the top surface of the source/drain feature facing away from the substrate;
removing a first portion of the semiconductor-containing dielectric layer to expose a first portion of the top surface of the source/drain feature while a second portion of the top surface of the source/drain feature remains covered by a second portion of the semiconductor-containing dielectric layer; and
forming a conductive feature on the exposed first portion of the top surface of the source/drain feature while the second portion of the top surface of the source/drain feature remains covered by the second portion of the first layer.

10. The method of claim 9 , wherein:
the substrate has a gate feature disposed on the substrate;
the forming of the etch stop layer forms the etch stop layer on the gate feature; and
the conductive feature extends through the etch stop layer to physically couple to the gate feature.

11. The method of claim 10 , wherein the forming of the etch stop layer forms the etch stop layer on a top surface of the gate feature and on opposing side surfaces of the gate feature.

12. The method of claim 9 , wherein the forming of the etch stop layer on the substrate includes forming the metal-containing dielectric layer directly on the semiconductor-containing dielectric layer.

13. The method of claim 12 , further comprising:
forming an interlayer dielectric layer directly on the metal-containing dielectric layer; and
forming a trench through the interlayer dielectric layer to expose a first portion of the metal-containing dielectric layer, and
wherein the removing of the first portion of the semiconductor-containing dielectric layer to expose the first portion of the top surface of the source/drain feature further includes removing the first portion of the metal-containing dielectric layer.

14. A method comprising:
forming a fin structure over a substrate, the fin structure having a first sidewall surface and an opposing second sidewall surface and a top surface extending from the first sidewall surface to the second sidewall surface;
forming a source/drain feature directly on the top surface of the fin structure, wherein the source/drain feature has a topmost surface facing away from the substrate;
forming a first etch stop layer on the source/drain feature and the fin structure such that the first etch stop layer physically contacts a side surface of the source/drain feature, the first sidewall surface of the fin structure and the second sidewall surface of the fin structure, wherein the forming of the first etch stop layer on the source/drain feature includes forming the first etch stop layer directly on the topmost surface of the source/drain feature;
forming a second etch stop layer disposed on the first etch stop layer over the source/drain feature, wherein the second etch stop layer is different in composition from the first etch stop layer;
removing a first portion of the first etch stop layer to expose a first portion of the topmost surface of the source/drain feature while a second portion of the topmost surface of the source/drain feature remains covered by a second portion of the first etch stop layer; and
forming a conductive feature on the exposed first portion of the topmost surface of the source/drain feature while the second portion of the topmost surface of the source/drain feature remains covered by the second portion of the first etch stop layer.

15. The method of claim 14 , further comprising:
forming a dielectric layer on the second etch stop layer disposed over the source/drain feature; and
forming a first conductive feature extending through the dielectric layer, the second etch stop layer, and the first etch stop layer to couple to the source/drain feature.

16. The method of claim 14 , wherein the first etch stop layer includes a silicon-containing dielectric (SCD) material, and the second etch stop layer includes a metal-containing dielectric (MCD) material.

17. The method of claim 16 , wherein the SCD material includes silicon and one of: oxygen, carbon, and nitrogen.

18. The method of claim 14 , wherein the first etch stop layer includes silicon, carbon and nitrogen.

19. The method of claim 14 , wherein the source/drain feature is at least partially embedded in the fin structure after the forming of the source/drain feature directly on the top surface of the fin structure.

20. The method of claim 14 , wherein the forming of the first etch stop layer on the source/drain feature and the fin structure includes depos

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tung Szu-Ping
• Wang Jen Hung
• Pan Shing-Chyang

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title