Avalon-to-Axi4 bus conversion method

Patent metadata

Field	Value
Publication number	US-11657011-B2
Application number	US-202017780190-A
Country	US
Kind code	B2
Filing date	Dec 9, 2020
Priority date	Feb 29, 2020
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

Disclosed is an Avalon-to-Axi4 bus conversion method, including: in case that an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, performing a logical process on the received Avalon_st bus data, and then outputting corresponding Axi4_st bus data; and in case that the Avalon bus is an Avalon_mm bus, receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus.

First claim

The invention claimed is:

1. An Avalon-to-Axi4 bus conversion method, comprising:
in case that an Avalon bus is a streaming mode of the Avalon bus (Avalon_st bus), receiving Avalon_st bus data, performing a logical process on the Avalon_st bus data, and then outputting corresponding streaming mode of an Axi4 bus (Axi4_st bus) data; and
in case that the Avalon bus is a memory mapping mode of the Avalon bus (Avalon_mm bus), receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus;
wherein the performing a logical process on the Avalon_st bus data and then outputting the corresponding streaming mode of the Axi4_st bus data comprises:
assigning values of a data packet end marker, data validity identifier, and device ready-state identifier in the Avalon_st bus data to corresponding interfaces of an Axi4_st bus;
performing high-low bit logic negation in units of bytes on data in the Avalon_st bus data, and then assigning a value to the corresponding interface of the Axi4_st bus; and
obtaining a valid byte position based on an invalid byte position in the Avalon_st bus data, and assigning a value at the valid byte position to the corresponding interface of the Axi4_st bus.

2. The Avalon-to-Axi4 bus conversion method according to claim 1 , wherein the signal transmitted by each channel of the Avalon_mm bus comprises a read instruction, an address to be read, and a burst length, or comprises a write instruction, an address to be written, and a burst length, or comprises a write instruction, data to be written, and a burst length.

3. The Avalon-to-Axi4 bus conversion method according to claim 1 , further comprising:
outputting a waitrequest signal to the Avalon_mm bus according to a depth parameter and data storage condition of the asynchronous FIFO.

4. The Avalon-to-Axi4 bus conversion method according to claim 3 , further comprising:
modifying the depth parameter of the asynchronous FIFO.

5. An Avalon-to-Axi4 bus conversion device, comprising:
a memory, configured to store a computer program; and
a processor, configured to execute the computer program to implement any steps of an Avalon-to-Axi4 bus conversion method, wherein the Avalon-to-Axi4 bus conversion method comprises:
in case that an Avalon bus is a streaming mode of the Avalon bus (Avalon_st bus), receiving Avalon_st bus data, performing a logical process on the Avalon_st bus data, and then outputting corresponding streaming mode of an Axi4 bus (Axi4_st bus) data; and
in case that the Avalon bus is a memory mapping mode of the Avalon bus (Avalon_mm bus), receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus;
wherein the performing a logical process on the Avalon_st bus data and then outputting the corresponding streaming mode of the Axi4_st bus data comprises:
assigning values of a data packet end marker, data validity identifier, and device ready-state identifier in the Avalon_st bus data to corresponding interfaces of an Axi4_st bus;
performing high-low bit logic negation in units of bytes on data in the Avalon_st bus data, and then assigning a value to the corresponding interface of the Axi4_st bus; and
obtaining a valid byte position based on an invalid byte position in the Avalon_st bus data, and assigning a value at the valid byte position to the corresponding interface of the Axi4_st bus.

6. The Avalon-to-Axi4 bus conversion device according to claim 5 , wherein the signal transmitted by each channel of the Avalon_mm bus comprises a read instruction, an address to be read, and a burst length, or comprises a write instruction, an address to be written, and a burst length, or comprises a write instruction, data to be written, and a burst length.

7. The Avalon-to-Axi4 bus conversion device according to claim 5 , wherein the Avalon-to-Axi4 bus conversion method further comprises:
outputting a waitrequest signal to the Avalon_mm bus according to a depth parameter and data storage condition of the asynchronous FIFO.

8. The Avalon-to-Axi4 bus conversion device according to claim 7 , wherein the Avalon-to-Axi4 bus conversion method further comprises:
modifying the depth parameter of the asynchronous FIFO.

9. A non-transitory computer-readable storage medium, having a computer program stored thereon which, when executed by a processor, implements any steps of an Avalon-to-Axi4 bus conversion method, wherein the Avalon-to-Axi4 bus conversion method comprises:
in case that an Avalon bus is a streaming mode of the Avalon bus (Avalon_st bus), receiving Avalon_st bus data, performing a logical process on the Avalon_st bus data, and then outputting corresponding streaming mode of an Axi4 bus (Axi4_st bus) data; and
in case that the Avalon bus is a memory mapping mode of the Avalon bus (Avalon_mm bus), receiving a signal transmitted by each channel of the Avalon_mm bus, framing and storing the signal in asynchronous First Input First Output (FIFO), and in case that a device corresponding to an Axi4 bus is ready, reading the signal from the asynchronous FIFO, and outputting the signal to a corresponding channel of the Axi4 bus according to a timing relationship of the Axi4 bus;
wherein the performing a logical process on the Avalon_st bus data and then outputting the corresponding streaming mode of the Axi4_st bus data comprises:
assigning values of a data packet end marker, data validity identifier, and device ready-state identifier in the Avalon_st bus data to corresponding interfaces of an Axi4_st bus;
performing high-low bit logic negation in units of bytes on data in the Avalon_st bus data, and then assigning a value to the corresponding interface of the Axi4_st bus; and
obtaining a valid byte position based on an invalid byte position in the Avalon_st bus data, and assigning a value at the valid byte position to the corresponding interface of the Axi4_st bus.

10. The non-transitory computer-readable storage medium according to claim 9 , wherein the signal transmitted by each channel of the Avalon_mm bus comprises a read instruction, an address to be read, and a burst length, or comprises a write instruction, an address to be written, and a burst length, or comprises a write instruction, data to be written, and a burst length.

11. The non-transitory computer-readable storage medium according to claim 9 , wherein the Avalon-to-Axi4 bus conversion method further comprises:
outputting a waitrequest signal to the Avalon_mm bus according to a depth parameter and data storage condition of the asynchronous FIFO.

12. The non-transitory computer-readable storage medium according to claim 11 , wherein the Avalon-to-Axi4 bus conversion method further comprises:
modifying the depth parameter of the asynchronous FIFO.

Assignees

• Inspur Suzhou Intelligent Technology Co Ltd

Inventors

• Guo Lei
• Zhang Jingdong
• Wang Jiangwei

Classifications

• G06F13/4239

  with asynchronous protocol · CPC title

• G06F13/4059 Primary

  where the synchronisation uses buffers, e.g. for speed matching between buses · CPC title

• G06F13/4013 Primary

  with data re-ordering, e.g. Endian conversion · CPC title