Multi-purpose interface for configuration data and user fabric data

Patent metadata

Field	Value
Publication number	US-10833679-B2
Application number	US-201816235984-A
Country	US
Kind code	B2
Filing date	Dec 28, 2018
Priority date	Dec 28, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a first integrated circuit die comprising embedded memory, programmable logic fabric, and first interface circuitry, wherein the first interface circuitry is coupled to a configuration data interface and a fabric data interface, wherein the configuration data interface couples to the embedded memory via a data register, and wherein the fabric data interface couples to the programmable logic fabric;
a second integrated circuit die comprising fabric support circuitry and second interface circuitry; and
a microbump interface configurable to connect the first integrated circuit die and the second integrated circuit die, wherein the microbump interface comprises a plurality of channels, and wherein a channel of the plurality of channels is configurable to exchange data with the programmable logic fabric and with the embedded memory.

2. The integrated circuit device of claim 1 , wherein the fabric data interface comprises a plurality of protocol blocks, and wherein a protocol block of a plurality of protocol blocks is associated with at least one channel of the plurality of channels.

3. The integrated circuit device of claim 2 , wherein the protocol blocks comprise a direct memory access protocol block, a memory mapped interface protocol block, a network on chip (NOC) protocol block, a streaming protocol block, a debug and trace protocol block, a fabric test protocol block, or an application specific interface protocol block, or any combination thereof.

4. The integrated circuit device of claim 1 , wherein a first channel of the plurality of channels comprises a first set of microbumps of the microbump interface, and a second channel of the plurality of channels comprises a second set of microbumps of the microbump interface.

5. The integrated circuit device of claim 1 , wherein the first interface circuitry is configurable to operate at an internal data rate, a first channel of the plurality of channels is configurable to operate at a microbump data rate larger than the internal data rate, and the first channel is configurable to perform a clocking adjustment to match the internal data rate to the microbump data rate.

6. The integrated circuit device of claim 5 , wherein the clocking adjustment comprises a double data rate (DDR) clocking, a quad data rate (QDR) clocking, or a xY interface clocking.

7. The integrated circuit device of claim 1 , wherein the embedded memory comprises a configuration random access memory (CRAM).

8. The integrated circuit device of claim 1 , wherein each channel comprises a first block configurable to exchange fabric data with the programmable logic fabric, a second block configurable to exchange configuration data with the embedded memory, and a multiplexer configurable to provide access from the first block or the second block to the microbump interface.

9. The integrated circuit device of claim 8 , wherein the fabric support circuitry of the second integrated circuit die comprises a circuit configurable to receive first data from the programmable logic fabric via the microbump interface and transmit second data to the programmable logic fabric via the microbump interface, and wherein the second integrated circuit die comprises retiming circuitry configurable to:
receive a source clock signal synchronized to the first data;
program delay circuitry of the second integrated circuit based on the source clock signal to produce a return clock signal; and
provide the return clock signal to the circuit, wherein the circuit is configurable to transmit the second data to the programmable logic fabric sampled by the return clock signal, and wherein the second data is received synchronously by the programmable logic fabric.

10. A method to reconfigure a programmable logic device, comprising:
selecting for reassignment a first channel of a microbump interface assigned to a fabric data interface that couples the microbump interface to programmable fabric, wherein the microbump interface couples a fabric die and a base die, the fabric die comprises the programmable fabric and a configuration memory, and wherein the programmable fabric comprises a first circuit design;
assigning the first channel to a configuration data interface that couples the microbump interface to the configuration memory of the fabric die, wherein the fabric die comprises first interface circuitry configurable to operate at an internal data rate, wherein the first channel is configurable to operate at a microbump data rate larger than the internal data rate, and wherein the first channel is configurable to perform a clocking adjustment to match the internal data rate to the microbump data rate; and
programming the programmable fabric by writing a fabric configuration bitstream to the configuration memory from the base die to the configuration memory through the first channel, wherein the fabric configuration bitstream comprises a second circuit design.

11. The method of claim 10 , comprising programming bitslice circuitry of the microbump interface based on a data rate of the first channel and a width of an internal bus that couples the microbump interface to the configuration memory.

12. The method of claim 10 , wherein the fabric configuration bitstream comprises a reconfiguration of a portion of the second circuit design.

13. The method of claim 12 , comprising performing at least one operation of the first circuit design on a second channel of the microbump interface while programming the portion of the programmable fabric.

14. The method of claim 10 , wherein the first circuit design performs at least one operation comprising receiving data from circuitry in the base die through a second channel of the microbump interface.

15. The method of claim 10 , comprising receiving the fabric configuration bitstream from a network on chip (NOC) circuitry of the base die, memory of the base die, or both.

16. An electronic device, comprising:
a fabric die that comprises:
programmable fabric;
configuration memory configurable to program the programmable fabric; and
first interface circuitry coupled to a microbump interface; and

a base die comprising second interface circuitry coupled to the microbump interface, wherein the microbump interface comprises a plurality of microbump data signals and a plurality of channels, wherein the plurality of channels is configurable to couple to the plurality of microbump data signals, and wherein a channel of the plurality of channels comprises a first block configurable to exchange fabric data with the programmable fabric, a second block configurable to exchange configuration data with an embedded memory, and a multiplexer configurable to provide access from the first block or the second block to the microbump interface.

17. The electronic device of claim 16 , wherein the channel of the plurality of channels is configurable to exchange data with the programmable fabric and the configuration memory.

18. The electronic device of claim 16 , comprising a data processing system comprising the fabric die and the base die.

19. The electronic device of claim 18 , wherein the data processing system is configurable to perform networking functions, data center functions, storage functions, communication functions, machine learning, video processing, voice recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, compute-in-memory, ASIC emulation, or spatial navigation, or any combination thereof.

Assignees

• Intel Corp

Inventors

• Clark Kevin
• Weber Scott J
• Ball James
• Gutala Ravi Prakash
• Dasu Aravind Raghavendra

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H03K19/1776 Primary

  for memories · CPC title

• G11C7/1078

  Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits · CPC title