Spacer structure for semiconductor device

Patent metadata

Field	Value
Publication number	US-11652157-B2
Application number	US-202217706339-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Aug 11, 2020
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, a first inner spacer layer formed in the fin structure and adjacent to the gate structure, and a second inner spacer layer extending through the first inner spacer layer.

First claim

What is claimed is:

1. A method, comprising:
forming a fin structure over a substrate, wherein the fin structure comprises a nanostructure;
forming a first inner spacer at an end portion of the nanostructure;
positioning the substrate at a first distance from a radical source to remove a portion of the nanostructure; and
positioning the substrate at a second distance, greater than the first distance, from the radical source to form a second inner spacer in contact with a front surface of the first inner spacer.

2. The method of claim 1 , further comprising forming a third inner spacer in contact with the first and second inner spacers.

3. The method of claim 1 , wherein positioning the substrate at the first distance from the radical source comprises positioning the substrate at the first distance between about 5 nm and about 50 nm from the radical source.

4. The method of claim 1 , wherein positioning the substrate at the second distance from the radical source comprises positioning the substrate at the second distance between about 60 nm and about 120 nm from the radical source.

5. The method of claim 1 , wherein positioning the substrate at the first distance from the radical source comprises performing an etching process using radicals generated by the radical source.

6. The method of claim 1 , wherein positioning the substrate at the first distance from the radical source comprises performing an etching process on the nanostructure at an etching rate greater than a deposition rate of the second inner spacer.

7. The method of claim 1 , wherein positioning the substrate at the second distance from the radical source comprises performing a deposition process using radicals generated by the radical source.

8. The method of claim 1 , wherein positioning the substrate at the second distance from the radical source comprises performing a deposition process to form the second inner spacer at a deposition rate greater than an etching rate of the second inner spacer.

9. The method of claim 1 , wherein positioning the substrate at the first distance from the radical source to remove the portion of the nanostructure comprises forming an opening in the removed portion of the nanostructure, and wherein positioning the substrate at the second distance from the radical source to form the second inner spacer comprises:
depositing a second inner spacer layer in the opening; and
removing a portion of the second inner spacer layer.

10. The method of claim 1 , further comprising:
positioning the substrate at a third distance from the radical source;
removing the nanostructure using radicals generated by the radical source to form an opening; and
forming a gate structure in the opening and in contact with the first and second inner spacers.

11. A method, comprising:
removing a portion of a fin structure to form a source/drain (S/D) opening, wherein the fin structure is formed over a substrate and comprises a nanostructure;
forming, via the S/D opening, a first inner spacer at an end portion of the nanostructure;
forming a S/D region in the S/D opening;
positioning the substrate at a first distance from a radical source to remove a portion of the nanostructure; and
positioning the substrate at a second distance, greater than the first distance, from the radical source to form, via the removed portion of the nanostructure, a second inner spacer in contact with a front surface of the first inner spacer.

12. The method of claim 11 , further comprising forming, via the removed portion of the nanostructure, a third inner spacer in contact with a side surface of the first inner spacer and in contact with the second inner spacer.

13. The method of claim 11 , wherein positioning the substrate at the first distance from the radical source comprises performing an etching process on the nanostructure at an etching rate greater than a deposition rate of the second inner spacer.

14. The method of claim 11 , wherein positioning the substrate at the second distance from the radical source comprises performing a deposition process to form the second inner spacer at a deposition rate greater than an etching rate of the second inner spacer.

15. The method of claim 11 , wherein forming the second inner spacer comprises:
depositing a second inner spacer layer in the removed portion of the nanostructure; and
removing a portion of the second inner spacer layer.

16. The method of claim 11 , further comprising:
positioning the substrate at a third distance from the radical source;
removing the nanostructure using radicals generated by the radical source to form an opening; and
forming a gate structure in the opening and in contact with the first and second inner spacers.

17. An apparatus, comprising:
a radical generator configured to:
receive a processing gas from a gas input;
receive a radio frequency (RF) discharging power from an RF source; and
convert the processing gas to radicals; and

a substrate holder configured to:
position a substrate at a first distance from the radical generator to remove a portion of a nanostructure: to expose a front surface of a first inner spacer, wherein the substrate comprises a fin structure comprising the nanostructure, and wherein the first inner spacer is formed at an end portion of the nanostructure; and
position the substrate at a second distance, greater than the first distance, from the radical generator to form a second inner spacer in contact with the front surface of the first inner spacer.

18. The apparatus of claim 17 , wherein the substrate holder is configured to position the substrate at the first distance between about 5 nm and about 50 nm from the radical generator, and wherein the substrate holder is configured to position the substrate at the second distance between about 60 nm and about 120 nm from the radical generator.

19. The apparatus of claim 17 , wherein in response to the substrate being positioned at the first distance from the radical generator, the apparatus is configured to perform an etching process using the radicals.

20. The apparatus of claim 17 , wherein in response to the substrate being positioned at the second distance from the radical generator, the apparatus is configured to perform a deposition process using the radicals.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lo Yi-Chen

Classifications

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title