Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA

Patent metadata

Field	Value
Publication number	US-11651111-B2
Application number	US-202017129250-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Sep 25, 2020
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to receive an incoming partial reconfiguration (PR) bitstream corresponding to a new PR persona to configure a region of the apparatus; perform, as part of a PR configuration sequence for the new PR persona, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the new PR persona.

First claim

What is claimed is:

1. An apparatus comprising:
a programmable integrated circuit (IC) comprising processing hardware circuitry to:
receive an incoming partial reconfiguration (PR) bitstream corresponding to a PR persona, wherein the incoming PR bitstream is to configure a region of the programmable IC; and
perform an implicit state clean process of the region of the programmable IC as part of a PR configuration sequence for the incoming PR bitstream, the implicit state clean process comprising:
a first clear operation to clear previously-set persona configuration bits in the region;
a set operation, performed subsequent to the first clear operation, to set new persona configuration bits in the region; and
a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the PR persona.

2. The apparatus of claim 1 , wherein the processing hardware circuitry to implement a security engine to manage the implicit state clean process, and wherein the security engine comprises a configuration manager and security enclave for the programmable IC.

3. The apparatus of claim 1 , wherein the first clear operation is performed using a persona-independent mask that is publicly authenticated.

4. The apparatus of claim 3 , wherein the persona-independent mask is not under control of a tenant of the programmable IC.

5. The apparatus of claim 1 , wherein the second clear operation is performed by loading the memory blocks with zeros.

6. The apparatus of claim 1 , wherein the PR bitstream implements a PR tenant workload.

7. The apparatus of claim 1 , wherein the apparatus comprises a hardware accelerator device comprising the programmable IC.

8. The apparatus of claim 7 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).

9. A method comprising:
receiving, by a programmable integrated circuit (IC), an incoming partial reconfiguration (PR) bitstream corresponding to a PR persona, wherein the PR bitstream is to configure a region of the programmable IC; and
performing, by the programmable IC, an implicit state clean process of the region of the programmable IC as part of a PR configuration sequence for the incoming PR bitstream, the implicit state clean process comprising:
a first clear operation to clear previously-set persona configuration bits in the region;
a set operation, performed subsequent to the first clear operation, to set new persona configuration bits in the region; and
a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the PR persona.

10. The method of claim 9 , wherein the programmable IC to implement a security engine to manage the implicit state clean process, and wherein the security engine comprises a configuration manager and security enclave for the programmable IC.

11. The method of claim 9 , wherein the first clear operation is performed using a persona-independent mask that is publicly authenticated, and wherein the persona-independent mask is not under control of a tenant of the programmable IC.

12. The method of claim 9 , wherein the second clear operation is performed by loading the memory blocks with zeros.

13. The method of claim 9 , wherein the PR bitstream implements a PR tenant workload.

14. The method of claim 9 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).

15. A non-transitory machine readable storage medium comprising instructions that, when executed, cause at least one processor to at least:
receive, by a programmable integrated circuit (IC) comprising the at least one processor, an incoming partial reconfiguration (PR) bitstream corresponding to a PR persona, wherein the PR bitstream is to configure a region of the programmable IC; and
perform, by the programmable IC, an implicit state clean process of the region of the programmable IC as part of a PR configuration sequence for the incoming PR bitstream, the implicit state clean process comprising:
a first clear operation to clear previously-set persona configuration bits in the region;
a set operation, performed subsequent to the first clear operation, to set new persona configuration bits in the region; and
a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation, the second clear operation performed using a persona-dependent mask corresponding to the new PR persona.

16. The non-transitory machine readable storage medium of claim 15 , wherein the programmable IC to implement a security engine to manage the implicit state clean process, and wherein the security engine comprises a configuration manager and security enclave for the programmable IC.

17. The non-transitory machine readable storage medium of claim 15 , wherein the first clear operation is performed using a persona-independent mask that is publicly authenticated, and wherein the persona-independent mask is not under control of a tenant of the programmable IC.

18. The non-transitory machine readable storage medium of claim 15 , wherein the second clear operation is performed by loading the memory blocks with zeros.

19. The non-transitory machine readable storage medium of claim 15 , wherein the PR bitstream implements a PR tenant workload.

20. The non-transitory machine readable storage medium of claim 15 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).

Assignees

• Intel Corp

Inventors

• Trivedi Alpa
• Weber Scott
• Schulz Steffen
• Koeberl Patrick

Classifications

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F2209/509

  Offload · CPC title

• H04L63/20

  for managing network security; network security policies in general (filtering policies H04L63/0227) · CPC title

• H04L9/008

  involving homomorphic encryption · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title