Methods and apparatus for unloading data from a configurable integrated circuit

Patent metadata

Field	Value
Publication number	US-2018367147-A1
Application number	US-201715625897-A
Country	US
Kind code	A1
Filing date	Jun 16, 2017
Priority date	Jun 16, 2017
Publication date	Dec 20, 2018
Grant date	—

Abstract

A system may include a host processor and a coprocessor for accelerating tasks received from the host processor. The coprocessor may include programmable circuitry organized into logic sectors. Each logic sector may have a dedicated local sector manager (LSM). The LSMs may be controlled by a secure device manager (SDM). The SDM may be coupled to data unloading circuitry for unloading configuration data from the coprocessor off onto the host processor. The unloading circuitry may include a circular first-in first-out (FIFO) buffer circuit that can be divided into multiple partitions to store configuration data from the various LSMs. The FIFO buffer circuit may be configured as an input FIFO in a configuration (loading) mode or as an output FIFO in a data unloading mode.

First claim

1 . An integrated circuit, comprising:
a plurality of logic regions; a controller circuit configured to transmit commands to the plurality of logic regions, the commands direct the plurality of logic regions to unload configuration data; a buffer circuit configured to receive the configuration data from at least two logic regions in the plurality of logic regions; and external pins that receive the configuration data from the buffer circuit.

2 . The integrated circuit of claim 1 , further comprising:
a plurality of local region manager circuits associated with the plurality of logic regions, wherein each of the local region manager circuits includes memory for storing the configuration data to be unloaded.

3 . The integrated circuit of claim 2 , further comprising:
a first multiplexer coupled between the controller circuit and the plurality of local region manager circuits; a configuration circuit for loading new configuration data into the plurality of logic regions; and a second multiplexer coupled between the controller circuit and the plurality of local region manger circuits.

4 . The integrated circuit of claim 3 , wherein the controller circuit is further configured to divide the buffer circuit into multiple partitions.

5 . The integrated circuit of claim 4 , further comprising:
third multiplexers that are coupled between the buffer circuit and the external pins.

6 . The integrated circuit of claim 5 , further comprising:
a fourth multiplexer that is coupled between the buffer circuit and the configuration circuit.

7 . The integrated circuit of claim 4 , wherein a first group of logic regions in the plurality of logic regions is coupled to a first data bus, and wherein a second group of logic regions in the plurality of logic regions is coupled to a second data bus that is different than the first data bus.

8 . The integrated circuit of claim 7 , further comprising:
additional multiplexers having inputs coupled to the first and second data buses and outputs coupled to the buffer circuit.

9 . The integrated circuit of 8 , further comprising:
configuration input pins that are coupled to the inputs of the additional multiplexers.

10 . The integrated circuit of claim 1 , wherein the buffer circuit is a configurable circular first-in first-out (FIFO) circuit.

11 . A method of operating an integrated circuit, the method comprising:
with a secure device manager, receiving an unload command; in response to receiving the unload command, using the secure device manager to configure unloading circuitry such that a buffer circuit in the unloading circuitry is coupled to external pins; synchronously offloading data from a plurality of logic sectors to the external pins via the buffer circuit; dividing the buffer circuit into multiple partitions; and with the partitions of the buffer circuit, receiving data from the plurality of logic sectors in parallel.

12 . The method of claim 11 , further comprising configuring the buffer circuit as an output first-in first-out (FIFO) circuit when offloading the data.

13 . The method of claim 12 , further comprising configuring the buffer circuit as an input FIFO circuit for receiving data to be loaded into the plurality of logic sectors.

14 . (canceled)

15 . The method of claim 11 , further comprising:
in response to determining that one of the partitions is full, directing the plurality of logic sectors to send data to another one of the partitions; and in response to determining that one of the partitions is empty, directing the buffer circuit to unload data from another one of the partitions.

16 . A non-transitory computer-readable storage medium comprising instructions for:
configuring a set of multiplexers so that a buffer circuit is coupled to external pins; dividing the buffer circuit into multiple partitions; and directing a plurality of local sector managers to offload configuration data to the external pins via the buffer circuit, wherein the local sector managers offload the configuration data to the multiple partitions of the buffer circuit in parallel.

17 . The non-transitory computer-readable storage medium of claim 16 , further comprising instructions for:
receiving a Joint Test Action Group (JTAG) read request command.

18 . The non-transitory computer-readable storage medium of claim 16 , further comprising instructions for:
directing a first selected local sector manager in a first group of the local sector managers to send its configuration data to one of the multiple partitions via a first data bus; and directing a second selected local sector manager in a second group of the local sector managers to send its configuration data to another one of the multiple partitions via a second data bus that is different than the first data bus.

19 . The non-transitory computer-readable storage medium of claim 18 , further comprising instructions for:
directing additional multiplexers to route the configuration data from the first and second data buses to the corresponding partitions in the buffer circuit.

20 . The non-transitory computer-readable storage medium of claim 16 , further comprising instructions for:
configuring the buffer circuit as an input first-in first-out (FIFO) circuit in a configuration mode for loading new configuration data into the plurality of local sector managers; and configuring the buffer circuit as an output first-in first-out (FIFO) circuit in an unloading mode during which the plurality of local sector managers offload the configuration data to the external pins via the buffer circuit.

21 . The integrated circuit of claim 1 , wherein the buffer circuit is operable in a configuration mode for loading new configuration data into the plurality of logic regions and an unloading mode for offloading the configuration data to the external pins.

Assignees

• Intel Corp

Inventors

• Khor Kok Wah
• Ho Eng Ling

Classifications

• H03K19/17756 Primary

  for partial configuration or partial reconfiguration · CPC title

• H03K19/1776

  for memories · CPC title