Sharing a JTAG interface among multiple partitions

Patent metadata

Field	Value
Publication number	US-10101387-B1
Application number	US-201715429008-A
Country	US
Kind code	B1
Filing date	Feb 9, 2017
Priority date	Feb 9, 2017
Publication date	Oct 16, 2018
Grant date	Oct 16, 2018

Abstract

An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via multiple logic signals. The JTAG system includes a JTAG interface receives the multiple logic signals. The JTAG system also includes a JTAG hub instantiated in the first partition and being communicatively coupled to the JTAG interface. The JTAG system further includes JTAG-based logic instantiated in the second partition. The integrated circuit device further includes an interface instantiated in the first partition configured to communicatively couple the JTAG hub to the JTAG-based logic.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a first partition and a second partition; and
a boundary scan system configured to control at least a portion of the integrated circuit device via a plurality of logic signals, wherein the boundary scan system comprises:
a boundary scan interface configured to receive the plurality of logic signals;
a boundary scan hub instantiated in the first partition and being communicatively coupled to the boundary scan interface;
boundary scan-based logic instantiated in the second partition; and
an interface instantiated in the first partition configured to communicatively couple the boundary scan hub to the instantiated boundary scan-based logic;
wherein the second partition is configured to be reconfigured by:
loading a partial reconfiguration file in the second partition while the first partition concurrently runs an application; and
instantiating the boundary scan-based logic in the second partition while the first partition concurrently runs the application in response to loading the partial reconfiguration file in the second partition.

2. The integrated circuit device of claim 1 , wherein the boundary scan-based logic comprises a system level debugging (SLD) endpoint.

3. The integrated circuit device of claim 2 , wherein the SLD endpoint comprises an In-System Sources and Probes (ISSP) interface, a SignalTap (STAP) interface, an In-System Memory Content Editor (ISMCE) interface, a Debug Bus Master interface, a Debug Packet Streamer interface, or a Microprocessor Debugger Module interface.

4. The integrated circuit device of claim 2 , wherein a partial reconfiguration region of the first partition comprises at least a portion of the boundary scan hub associated with providing the boundary scan interface to the SLD endpoint and the interface.

5. The integrated circuit device of claim 4 , wherein the boundary scan interface is communicatively coupled to one or more electronic design automation (EDA) software tools configured to recompile the partial reconfiguration region in response to removing the SLD endpoint from the second partition.

6. The integrated circuit device of claim 4 , wherein the boundary scan interface is communicatively coupled to one or more electronic design automation (EDA) software tools configured to reconfigure the partial reconfiguration region in response to adding a second SLD endpoint to the second partition.

7. A boundary scan system comprising:
a boundary scan interface of an integrated circuit configured to receive a plurality of boundary scan logic signals;
a boundary scan hub instantiated in a first partition of the integrated circuit and communicatively coupled to the boundary scan interface;
a system level debugging (SLD) endpoint instantiated in a second partition of the integrated circuit; and
an SLD endpoint interface instantiated in the first partition configured to communicatively couple the boundary scan hub to the instantiated SLD endpoint;
wherein the second partition is configured to recompile while the first partition concurrently runs an application, wherein recompiling the second partition comprises one or more of maintaining instantiation of the instantiated SLD endpoint, modifying the instantiated SLD endpoint, removing the instantiated SLD endpoint, or instantiating an additional SLD endpoint in the second partition.

8. The boundary scan system claim 7 , comprising a computing device communicatively coupled to the boundary scan interface.

9. The boundary scan system claim 8 , wherein the computing device comprises one or more electronic design automation (EDA) software tools.

10. The boundary scan system claim 9 , wherein the one or more EDA software tools are configured to automatically reconfigure at least a portion of the boundary scan hub and the SLD endpoint interface in response to removing the instantiated SLD endpoint from the second partition or instantiating the additional SLD endpoint in the second partition.

11. The boundary scan system claim 10 , wherein automatically reconfiguring at least the portion of the boundary scan hub and the SLD endpoint interface comprises compiling at least the portion of the boundary scan hub and the SLD endpoint interface while concurrently running one or both of the application on the first partition or an additional application on the second partition.

12. The boundary scan system claim 10 , wherein the one or more EDA software tools are configured to automatically reconfigure at least the portion of the boundary scan hub and the SLD endpoint interface without altering the application running on the second partition.

13. A method comprising:
creating a first partition in an integrated circuit;
instantiating a boundary scan hub in the first partition, the boundary scan hub being communicatively coupled to a boundary scan interface;
creating a second partition in the integrated circuit;
instantiating boundary scan-based logic in the second partition;
instantiating an interface in the first partition that is configured to communicatively couple the boundary scan hub to the instantiated boundary scan-based logic; and
recompiling the second partition while concurrently running an application on the first partition, wherein recompiling the second partition comprises one or more of maintaining instantiation of the instantiated boundary scan-based logic, modifying the instantiated boundary scan-based logic, removing the instantiated boundary scan-based logic, or instantiating additional boundary scan-based logic in the second partition.

14. The method of claim 13 , wherein the boundary scan-based logic comprises a system level debugging (SLD) endpoint.

15. The method of claim 14 , wherein a partial reconfiguration region of the first partition comprises at least a portion of the boundary scan hub associated with providing the boundary scan interface to the SLD endpoint and the interface.

16. The method of claim 15 , comprising recompiling the partial reconfiguration region in response to removing the SLD endpoint from the second partition.

17. The method of claim 16 , wherein recompiling the partial reconfiguration region comprises compiling at least a portion of the partial reconfiguration region associated with providing the boundary scan interface to the SLD endpoint while concurrently running one or both of the application on the first partition or an additional application on the second partition.

18. The method of claim 15 , comprising recompiling the partial reconfiguration region in response to adding a second SLD endpoint to the second partition.

19. The method of claim 18 , wherein recompiling the partial reconfiguration region comprises compiling at least a portion of the partial reconfiguration region associated with providing the boundary scan interface to the second SLD endpoint while concurrently running one or both of the application on the first partition or an additional application on the second partition.

20. The method of claim 13 , wherein instantiating one or more of the boundary scan hub, the boundary scan-based logic, or the interface comprises configuring one or both of a reconfigurable logic element or routing wire in the respective first partition or second partition to generate one or more instances of the one or more of the boundary scan hub, the boundary scan-based logic, or the interface.

Assignees

• Intel Corp

Inventors

• Iyer Mahesh A
• Peng Yi

Classifications

• G01R31/31726

  Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/31705

  Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544) · CPC title

• G01R31/3172 Primary

  Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing · CPC title

• G01R31/318563

  Multiple simultaneous testing of subparts · CPC title