Silicon oxide silicon nitride stack stair step etch

US11646207B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11646207-B2
Application numberUS-201816766256-A
CountryUS
Kind codeB2
Filing dateNov 29, 2018
Priority dateNov 30, 2017
Publication dateMay 9, 2023
Grant dateMay 9, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiO2 layer and etching a SiN layer. Etching a SiO2 layer comprises flowing a SiO2 etching gas into the plasma processing chamber, wherein the SiO2 etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF6 and NF3, generating a plasma from the SiO2 etching gas, providing a bias, and stopping the SiO2 layer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, comprising a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a stair-step structure in a stack on a substrate in a plasma processing chamber, wherein the stack comprises a plurality of silicon oxide and silicon nitride bilayers under a mask, comprising at least one stair step cycle, wherein each stair step cycle comprises: trimming the mask; and etching the stack in a plurality of cycles, wherein each cycle comprises: etching a SiO 2 layer, comprising: flowing a SiO 2 etching gas into the plasma processing chamber, wherein the SiO 2 etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF 6 and NF 3 ; generating a plasma from the SiO 2 etching gas; providing a bias; and stopping the SiO 2 layer etch; and etching a SiN layer, wherein the SiN layer is selectively etched with respect to the SiO 2 layer and the mask, comprising: flowing a SiN etching gas into the plasma processing chamber, wherein the SiN etching gas comprises a hydrofluorocarbon and oxygen; generating a plasma from the SiN etching gas; providing a bias; and stopping the SiN layer etch. 2. The method, as recited in claim 1 , wherein the SiO 2 etching gas is oxygen free. 3. The method, as recited in claim 2 , wherein the SiO 2 etching gas comprises SF 6 and NF 3 . 4. The method, as recited in claim 2 , wherein the SiO 2 etching gas comprises SF 6 . 5. The method, as recited in claim 1 , wherein the method comprises at least twenty stair step cycles. 6. The method, as recited in claim 1 , wherein the inert bombardment gas is He. 7. The method, as recited in claim 1 , wherein the hydrofluorocarbon in the SiN etching gas is at least one of CH 2 F 2 , CH 3 F, and CHF 3 . 8. The method, as recited in claim 1 , wherein the bias during the etching of the SiN layer has a magnitude that is greater than or equal to a magnitude of the bias during the etching of the SiO 2 layer. 9. The method, as recited in claim 1 , wherein the bias during the etching of the SiN layer has a magnitude that is between 150 to 400 volts inclusive and the bias during the etching of the SiO 2 layer has a magnitude that is less than 150 volts. 10. The method, as recited in claim 1 , further comprising providing a pressure of greater than 30 mTorr during the etching of the SiN layer and providing a pressure of less than 20 mTorr during the etching of the SiO 2 layer. 11. The method, as recited in claim 1 , wherein the etching the SiN layer is less than 10 seconds for each cycle and the etching the SiO 2 layer is less than 10 seconds for each cycle. 12. The method, as recited in claim 1 , wherein the etching the stack comprises three to ten cycles. 13. The method, as recited in claim 1 , wherein the stack comprises more than 60 bilayers. 14. The method, as recited in claim 1 , wherein the flowing a SiN etching gas into the plasma processing chamber flows the hydrofluorocarbon through a center feed and a side feed, wherein the center feed includes one or more nozzles and the side feed includes one or more nozzles that are closer to sides of the substrate than a center of the substrate. 15. The method, as recited in claim 14 , wherein the one or more nozzles of the side feed flow hydrofluorocarbon in a direction from the sides of the substrate towards the center of the substrate. 16. The method, as recited in claim 1 , wherein the etching of the SiN layer has a SiN to SiO 2 etch selectivity in the range of 2:1 to 4:1. 17. The method, as recited in claim 16 , wherein the SiO 2 etch does not selectively etch the SiO 2 layer with respect to the SiN layer. 18. The method, as recited in claim 1 , wherein the SiO 2 etching gas comprises SF 6 and NF 3 . 19. The method, as recited in claim 1 , wherein the SiO 2 etching gas comprises SF 6 .

Assignees

Inventors

Classifications

  • H10P50/283Primary

    by chemical means · CPC title

  • using masks for insulating materials · CPC title

  • H10P50/242Primary

    of Group IV materials · CPC title

  • by chemical means · CPC title

  • characterised by the boundary region between the core and peripheral circuit regions · CPC title

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What does patent US11646207B2 cover?
A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiO2 layer and etching a SiN layer. Etching a SiO2 layer comprises flowing a SiO2 etching gas i…
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10P50/283. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 09 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).