Heterolithic microwave integrated circuits including gallium-nitride devices on intrinsic semiconductor

Patent metadata

Field	Value
Publication number	US-11640960-B2
Application number	US-202117344057-A
Country	US
Kind code	B2
Filing date	Jun 10, 2021
Priority date	Jan 19, 2018
Publication date	May 2, 2023
Grant date	May 2, 2023

Abstract

A number of integrated circuits and methods of manufacturing the integrated circuits are described. An integrated circuit can include different semiconductor devices formed from different semiconductor systems in different regions over the same substrate. The integrated circuit can also include bulk regions of low-loss electrically-insulating material extending through the substrate and located between the different semiconductor regions. Passive RF circuit elements can be formed on the low-loss electrically-insulating material.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a first region of the integrated circuit, the first region containing a diode formed on a substrate from a first semiconductor material of a first base elemental composition that is common with the substrate;
a second region of the integrated circuit, the second region containing a transistor comprising gallium-oxide formed over the substrate from a second semiconductor material that is different than the first semiconductor material of the first base elemental composition; and
a third region of the integrated circuit containing an electrically-insulating dielectric material.

2. The integrated circuit of claim 1 , wherein the electrically-insulating dielectric material extends through the substrate and separates the substrate between the first region and the second region.

3. The integrated circuit of claim 1 , wherein the diode comprises a p-i-n or n-i-p diode.

4. The integrated circuit of claim 1 , further comprising an intrinsic region of the first semiconductor material located between the second semiconductor material and the substrate in the second region.

5. The integrated circuit of claim 1 , wherein:
the first semiconductor material has a base elemental composition of silicon; and
the second semiconductor material comprises gallium-nitride material.

6. The integrated circuit of claim 1 , wherein the transistor comprises a high-electron-mobility transistor.

7. The integrated circuit of claim 1 , further comprising at least a portion of a conductive interconnect formed over the third region.

8. The integrated circuit of claim 1 , further comprising at least a portion of a passive circuit element formed over the third region.

9. The integrated circuit of claim 8 , wherein the passive circuit element comprises an inductor.

10. The integrated circuit of claim 1 , further comprising a ground plane formed on a back side of the substrate below the first region, second region, and third region.

11. The integrated circuit of claim 1 , further comprising a passivation layer formed over the first region, second region, and third region.

12. The integrated circuit of claim 1 , wherein the electrically-insulating dielectric material comprises glass.

13. The integrated circuit of claim 1 , further comprising doped region of the first semiconductor material under the second semiconductor material in the second region.

14. A method of manufacturing an integrated circuit, the method comprising:
forming a first semiconductor device from a first semiconductor material in a first region of a wafer;
forming a second semiconductor material on the first semiconductor material in a second region of the wafer, the second semiconductor material having a different base elemental composition than the first semiconductor material;
forming a second semiconductor device comprising gallium-oxide formed from the second semiconductor material;
etching a cavity in a third region of the wafer;
filling the cavity with an electrically-insulating material;
planarizing the electrically-insulating material; and
removing a portion of a backside of the wafer to expose the electrically-insulating material.

15. The method of claim 14 , wherein:
forming the first semiconductor device comprises forming a diode; and
forming the second semiconductor device comprises forming a transistor.

16. The method of claim 14 , wherein:
the first semiconductor material has a base elemental composition of silicon; and
the second semiconductor material comprises gallium-nitride material.

17. The method of claim 14 , wherein forming the second semiconductor material comprises epitaxially growing the second semiconductor material on the first semiconductor material.

18. The method of claim 14 , further comprising covering the second semiconductor material with a protective layer before filling the cavity.

19. The method of claim 18 , wherein filling the cavity comprises forcing the electrically-insulating material into the cavity under pressure.

20. The method of claim 14 , further comprising forming a conductive interconnect over the electrically-insulating material in the third region.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Boles Timothy E
• Struble Wayne Mack

Classifications

• H10P14/2908

  Nitrides · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W44/20 Primary

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title