Semiconductor device formed on SOI substrate

Patent metadata

Field	Value
Publication number	US-11640938-B2
Application number	US-202117460998-A
Country	US
Kind code	B2
Filing date	Aug 30, 2021
Priority date	Aug 31, 2020
Publication date	May 2, 2023
Grant date	May 2, 2023

Abstract

A semiconductor device is disclosed. The semiconductor device includes impurity regions formed in surface portions of a substrate, gate structures formed on surface portions of the substrate between the impurity regions, a first insulating layer formed on the impurity regions and the gate structures, first wiring patterns formed on the first insulating layer, and first contact patterns connecting the impurity regions and the first wiring patterns through the first insulating layer, and the first wiring patterns are arranged in a zigzag shape.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a plurality of impurity regions formed in surface portions of a substrate, the impurity regions being arranged in a first direction and extending parallel with one another in a second direction perpendicular to the first direction;
a plurality of gate structures formed on surface portions of the substrate between the impurity regions and extending parallel to the impurity regions;
a first insulating layer formed on the impurity regions and the gate structures;
a plurality of first wiring patterns formed on the first insulating layer and extending parallel to the impurity regions; and
a plurality of first contact patterns connecting the impurity regions and the first wiring patterns through the first insulating layer and extending parallel to the impurity regions,
wherein the first wiring patterns are arranged in a zigzag shape in the first direction.

2. The semiconductor device of claim 1 , wherein the first contact patterns have a length shorter than a length of the first wiring patterns.

3. The semiconductor device of claim 2 , wherein the first contact patterns are arranged in a zigzag shape in the first direction.

4. The semiconductor device of claim 2 , wherein the impurity regions have a length shorter than that of the gate structures.

5. The semiconductor device of claim 1 , wherein the substrate comprises a lower semiconductor layer, an upper semiconductor layer, and a buried insulating layer disposed between the lower semiconductor layer and the upper semiconductor layer, and
the impurity regions are formed in surface portions of the upper semiconductor layer.

6. The semiconductor device of claim 5 , further comprising:
a well region formed in the upper semiconductor layer,
wherein the impurity regions are formed on the well region.

7. The semiconductor device of claim 6 , further comprising:
a device isolation pattern formed on the buried insulating layer and configured to define the well region.

8. The semiconductor device of claim 5 , further comprising:
a connecting structure connected with end portions of the gate structures and extending in the first direction; and
a gate contact region connected with an edge portion of the connecting structure.

9. The semiconductor device of claim 8 , further comprising:
a well region formed in the substrate; and
a well contact region connected with the well region,
wherein the impurity regions are formed on the well region, and
the connecting structure is formed on the well contact region.

10. The semiconductor device of claim 9 , further comprising:
a device isolation pattern formed on the buried insulating layer and configured to define the well region and the well contact region.

Assignees

• Db Hitek Co Ltd

Inventors

• Lim Ki Won
• Jung Jin Hyo
• Kim Hae Taek
• Eom Seung Hyun
• Koo Ja Geon
• Lee Hyun Joong
• Lee Sang Yong

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D84/0149 Primary

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title