Non-volatile memory array

Patent metadata

Field	Value
Publication number	US-10868023-B2
Application number	US-201916265301-A
Country	US
Kind code	B2
Filing date	Feb 1, 2019
Priority date	Feb 2, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A non-volatile memory array includes gate structures disposed on a substrate, each of the gate structures including a tunneling oxide layer positioned on the substrate, a floating gate positioned on the tunneling oxide layer and being arranged along a first direction on the tunneling oxide layer, sidewall gates disposed on sidewalls of the floating gate, extending in the first direction and being spaced apart from each other, and a gate dielectric layer interposed between the floating gate and the sidewall gates, bit lines disposed over the substrate, each extending in a second direction to intersect the sidewall gates, a drain region positioned in an upper portion of the substrate, the drain region overlapping, and being electrically connected to, the one of the bit lines, and a source line positioned between adjacent sidewall gates, the source line extending in the first direction and being buried in the substrate.

First claim

What is claimed is:

1. A non-volatile memory array comprising:
a plurality of gate structures disposed on a substrate such that each gate structure is a member of at least one pair of adjacent gate structures, each of the gate structures including
a tunneling oxide layer positioned on the substrate,
a plurality of floating gates positioned on the tunneling oxide layer, each floating gate being arranged along a first direction on the tunneling oxide layer,
a sidewall gate extending in the first direction and disposed on sidewalls of the plurality of floating gates, and
a gate dielectric layer interposed between the floating gate and the sidewall gates, the sidewall gates of each gate structure spaced apart from each other;

a plurality of bit lines disposed over the substrate, each extending in a second direction to intersect the sidewall gate of each of the plurality of gate structures;
a drain region positioned in an upper surface portion of the substrate, the drain region overlapping one of the bit lines and being electrically connected to the one of the bit lines; and
a source line positioned between the sidewall gates of each pair of adjacent gate structures, the source line extending in the first direction and being buried in the substrate,
wherein the sidewall gates of each pair of gate structures of the plurality of adjacent gate structures are arranged at least partially on the source line such that charge travels between the source line and the sidewall gates of the pair of adjacent gate structures due to a tunneling effect which occurs at the tunneling oxide layer interposed between the source line and the sidewall gates of the pair of gate structures.

2. The non-volatile memory array of claim 1 , wherein the source line includes n-type conductivity dopants.

3. The non-volatile memory array of claim 1 , further comprising a first contact plug configured to connect one of the bit lines to the drain region.

4. The non-volatile memory array of claim 1 , wherein the gate dielectric layer has an ONO structure having an oxide layer, a nitride layer and an oxide layer sequentially stacked on the floating gates.

5. The non-volatile memory array of claim 1 , wherein each of the gate structures further includes spacers disposed on sidewalls of the sidewall gates.

Assignees

• Db Hitek Co Ltd

Inventors

• Lee Jun Ho

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title