Semiconductor device and method for manufacturing semiconductor device with low-permittivity layers

Patent metadata

Field	Value
Publication number	US-10879165-B2
Application number	US-201615762172-A
Country	US
Kind code	B2
Filing date	Sep 2, 2016
Priority date	Oct 16, 2015
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A semiconductor device in which the generation of a distortion of a signal is suppressed, and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes a transistor region in which a field effect transistor is provided; and an interconnection region in which a metal layer electrically connected to the field effect transistor is provided. The interconnection region includes an insulating layer provided between the metal layer and a substrate, and a low-permittivity layer provided in the insulating layer below the metal layer and having a lower permittivity than the insulating layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a transistor region in which a field effect transistor is provided; and
an interconnection region comprising a first metal layer and a second metal layer,
wherein the interconnection region includes:
an interlayer insulating layer provided above a substrate, wherein the interlayer insulating layer includes a plurality of insulating layers;
a first low-permittivity layer provided in the interlayer insulating layer directly below the first metal layer; and
a second low-permittivity layer provided in the interlayer insulating layer directly below the second metal layer, wherein:
the first metal layer is formed on a first insulating layer of the plurality of insulating layers and is electrically connected to the field effect transistor,
the second metal layer is formed on a second insulating layer of the plurality of insulating layers and is electrically connected to the field effect transistor,
each of the first and second low-permittivity layers comprise a material having a lower permittivity than the interlayer insulating layer,
the first low-permittivity layer and the second low-permittivity layer do not overlap in a plan view, and
each of the first low-permittivity layer and the second low-permittivity layer extends across the plurality of insulating layers.

2. The semiconductor device according to claim 1 , wherein the first and second low-permittivity layers are arranged in a striped fashion.

3. The semiconductor device according to claim 1 , wherein the first and second low-permittivity layers are arranged in a zigzag fashion.

4. The semiconductor device according to claim 1 , wherein one of the first and second low-permittivity layers is provided in each of the insulating layers.

5. The semiconductor device according to claim 4 , wherein the first and second low-permittivity layers are arranged in a zigzag fashion in the plan view.

6. The semiconductor device according to claim 1 , wherein the first and second low-permittivity layers are provided to pierce up to the substrate.

7. The semiconductor device according to claim 1 , wherein an upper-side metal layer is further provided on the first metal layer via an inter-metal insulating layer, and
wherein an inter-metal low-permittivity layer of a material having a lower permittivity than the inter-metal insulating layer is provided in the inter-metal insulating layer between the first metal layer and the upper-side metal layer.

8. The semiconductor device according to claim 1 , wherein at least one of the first and second low-permittivity layers is provided at least in a projection region of the first metal layer in the plan view.

9. The semiconductor device according to claim 1 , wherein the first metal layer is an interconnection electrically connected to the field effect transistor.

10. The semiconductor device according to claim 1 ,
wherein either of an upper end and a lower end of the each of the first and second low-permittivity layers are provided in a same layer.

11. The semiconductor device according to claim 1 , wherein the field effect transistor is associated with a radio frequency device.

12. A method for manufacturing a semiconductor device, comprising:
forming a field effect transistor in a transistor region;
filling, with an interlayer insulating layer, an interconnection region comprising a first metal layer and a second metal layer, wherein the interlayer insulating layer is provided above a substrate, wherein the interlayer insulating layer includes a plurality of insulating layers;
forming, in the interlayer insulating layer directly below the first metal layer, a first low-permittivity layer; and
forming, in the interlayer insulating layer directly below the second metal layer, a second low-permittivity layer, wherein:
the first metal layer is formed on a first insulating layer of the plurality of insulating layers and is electrically connected to the field effect transistor,
the second metal layer is formed on a second insulating layer of the plurality of insulating layers and is electrically connected to the field effect transistor,
each of the first and second low-permittivity layers comprise a material having a lower permittivity than the interlayer insulating layer,
the first and second low-permittivity layers do not overlap in a plan view, and
each of the first and second low-permittivity layers extends across the plurality of insulating layers.

Assignees

• Sony Corp

Inventors

• Saka Naoki

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title