Methods and systems to enhance process uniformity

US11637002B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11637002-B2
Application numberUS-201414554250-A
CountryUS
Kind codeB2
Filing dateNov 26, 2014
Priority dateNov 26, 2014
Publication dateApr 25, 2023
Grant dateApr 25, 2023

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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A semiconductor processing chamber may include a remote plasma region, and a processing region fluidly coupled with the remote plasma region. The processing region may be configured to house a substrate on a support pedestal. The support pedestal may include a first material at an interior region of the pedestal. The support pedestal may also include an annular member coupled with a distal portion of the pedestal or at an exterior region of the pedestal. The annular member may include a second material different from the first material.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor processing chamber comprising: a remote plasma region; and a processing region fluidly coupled with the remote plasma region, wherein: the processing region is configured to house a substrate on a support pedestal, the support pedestal comprises aluminum at an interior region of the pedestal, the support pedestal defines at least one recessed ledge on which an annular member is seated, the recessed ledge is defined in a top surface of the support pedestal configured to support a substrate, the annular member is coupled with a distal portion of the pedestal and maintains contact with the pedestal along all interior surfaces of the annular member, the annular member extends vertically above an uppermost surface of the support pedestal, the uppermost surface is configured to contact the substrate, and the annular member comprises aluminum plated with a second material comprising nickel or platinum, wherein the second material is not disposed on surfaces of the annular member in contact with the support pedestal. 2. The semiconductor processing chamber of claim 1 , wherein the annular member extends along an external edge of the pedestal towards a stem region of the pedestal. 3. The semiconductor processing chamber of claim 1 , wherein the annular member is coupled with the support pedestal at an edge region beyond the dimensions of a centrally located substrate region. 4. The semiconductor processing chamber of claim 1 , wherein the processing region is at least partially defined by a sidewall and wherein the sidewall comprises the second material. 5. The semiconductor processing chamber of claim 4 , wherein a sidewall heating element is embedded in the sidewall adjacent the processing region and proximate a showerhead defining the processing region from above. 6. The semiconductor processing chamber of claim 5 , wherein the support pedestal further comprises a pedestal temperature control, wherein the pedestal temperature control is configured to maintain the pedestal at a first temperature, wherein the sidewall heating element is configured to maintain the annular member at a second temperature, and wherein the second temperature is greater than the first temperature. 7. A semiconductor processing chamber comprising: a remote plasma region; and a processing region fluidly coupled with the remote plasma region, wherein: the processing region is at least partially defined by each of a showerhead, a substrate support pedestal comprising a first material, and a sidewall, the sidewall includes a liner on an interior chamber surface comprising a second material different from the first material, wherein the substrate support pedestal comprises a platform coupled with a stem, wherein the liner is disposed on the sidewall from the showerhead to a position in line with a location where the platform is coupled with the stem when the pedestal is in a raised operational position, and wherein the liner does not extend a full length of the sidewall defining the processing region, and a resistive heater is embedded in the sidewall adjacent the liner and within one inch of the showerhead. 8. The semiconductor processing chamber of claim 7 , wherein the pedestal comprises a temperature control, and wherein the temperature control is configured to maintain a substrate temperature at least 20° C. below a sidewall temperature maintained by the resistive heater. 9. The semiconductor processing chamber of claim 1 , wherein the support pedestal comprises a platform coupled with a stem, and wherein the annular member is maintained on the platform without extending to the stem. 10. The semiconductor processing chamber of claim 1 , wherein the support pedestal and annular member are configured to be vertically moveable. 11. The semiconductor processing chamber of claim 7 , wherein the liner comprises nickel or platinum. 12. A semiconductor processing chamber comprising: a remote plasma region; and a processing region fluidly coupled with the remote plasma region, wherein: the processing region is configured to house a substrate on a support pedestal, the support pedestal comprises a first material at an interior region of the pedestal, the support pedestal comprises an annular member coupled with a distal portion of the pedestal and extending vertically above an uppermost surface of the support pedestal to a height configured to be above a height of a substrate positioned on the support pedestal, and the annular member comprises the first material plated with a second material on surfaces of the annular member excluding surfaces of the annular member in contact with the support pedestal, wherein the second material comprises nickel or platinum. 13. The semiconductor processing chamber of claim 1 , wherein the second material is platinum. 14. The semiconductor processing chamber of claim 7 , wherein: the substrate support pedestal comprises aluminum at an interior region of the pedestal, the support pedestal defines at least one recessed ledge on which an annular member is seated, the recessed ledge is defined in a top surface of the support pedestal configured to support a substrate, the annular member is coupled with a distal portion of the pedestal, the annular member extends vertically above an uppermost surface of the support pedestal to a height configured to be above a height of a substrate positioned on the support pedestal, and the uppermost surface is configured to contact the substrate. 15. The semiconductor processing chamber of claim 14 , wherein the annular member comprises aluminum plated with nickel. 16. The semiconductor processing chamber of claim 14 , wherein the annular member comprises a platinum coating. 17. The semiconductor processing chamber of claim 1 , wherein the annular member extends about a backside of a support platter of the substrate support pedestal, and extends to a location partially along a stem of the substrate support pedestal. 18. The semiconductor processing chamber of claim 14 , wherein the annular member maintains contact with the pedestal along all interior surfaces of the annular member. 19. The semiconductor processing chamber of claim 12 , wherein the annular member maintains contact with the pedestal along all interior surfaces of the annular member. 20. The semiconductor processing chamber of claim 7 , wherein the support pedestal comprises a temperature control and an annular member coupled with a distal portion of the support pedestal; wherein the pedestal temperature control is configured to maintain the support pedestal at a first temperature; and wherein the resistive heater is configured to maintain the annular member at a second temperature greater than the first temperature.

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What does patent US11637002B2 cover?
A semiconductor processing chamber may include a remote plasma region, and a processing region fluidly coupled with the remote plasma region. The processing region may be configured to house a substrate on a support pedestal. The support pedestal may include a first material at an interior region of the pedestal. The support pedestal may also include an annular member coupled with a distal port…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P72/0421. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 25 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).