Self-isolating output driver

Patent metadata

Field	Value
Publication number	US-11626876-B2
Application number	US-202117393844-A
Country	US
Kind code	B2
Filing date	Aug 4, 2021
Priority date	Aug 14, 2020
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

Push-pull integrated circuit output drivers may interfere with communication by other entities on a bus when an integrated circuit is powered down. When there is no power and/or when the bonding pad is externally driven above the internal supply voltage, the substrate/body/well of the p-channel field effect transistor (PFET) of the output driver is biased to prevent its drain diode from becoming forward biased thereby preventing interference with communication on the bus. Also, when there is no power, driver is powered down or pull up is disabled, the gate of the driver PFET is driven to a voltage that ensures the driver PFET remains off when the bonding pad is externally driven above the internal supply voltage.

First claim

What is claimed is:

1. An integrated circuit, comprising:
an output driver configured to transmit signals on a bus via a pad while the integrated circuit is in an operational mode, the output driver including a first transistor having a direct current (DC) connection to the pad; and
isolation circuitry to, while the integrated circuit is in a non-operational mode and based on a first voltage level on the pad and a second voltage level on a power supply used by the output driver, select a one of the first voltage level and the second voltage level to apply to at least one terminal of the first transistor.

2. The integrated circuit of claim 1 , wherein the isolation circuitry is configured to select the first voltage level in response to the first voltage level meeting a first criteria.

3. The integrated circuit of claim 2 , wherein the first criteria is based on the first voltage level exceeding the second voltage level.

4. The integrated circuit of claim 3 , wherein the first transistor is a p-channel field effect transistor (PFET).

5. The integrated circuit of claim 2 , wherein the first transistor includes a control terminal and the first voltage level is applied to the control terminal based on the first voltage level meeting the first criteria.

6. The integrated circuit of claim 2 , wherein the first transistor includes a body terminal and the first voltage level is applied to the body terminal based on the first voltage level meeting the first criteria.

7. The integrated circuit of claim 1 , wherein the isolation circuitry further comprises:
comparator circuitry to provide, to switching circuitry, an indicator of whether the first voltage level exceeds the second voltage level.

8. An integrated circuit, comprising:
a transistor, a first terminal of the transistor being DC connected to a first external terminal of the integrated circuit and having a first variable voltage level, a second terminal of the transistor being DC connected to a power supply of the integrated circuit and having a second variable voltage level; and
switching circuitry configured to provide, while the integrated circuit is in a non-operational mode and based on the first variable voltage level and the second variable voltage level, and to a third terminal of the transistor, a one of the first variable voltage level and the second variable voltage level.

9. The integrated circuit of claim 8 , wherein the switching circuitry is to provide, to the third terminal of the transistor, the first variable voltage level in response to the first variable voltage level exceeding the second variable voltage level.

10. The integrated circuit of claim 8 , wherein the switching circuitry is to provide, to the third terminal of the transistor, the second variable voltage level in response to the first variable voltage level being less than the second variable voltage level.

11. The integrated circuit of claim 8 , further comprising:
a comparator circuit to provide an indicator of whether the first variable voltage level is greater than the second variable voltage level.

12. The integrated circuit of claim 11 , wherein the switching circuitry is to provide, to a comparator circuit power supply, the first variable voltage level in response to the first variable voltage level exceeding the second variable voltage level.

13. The integrated circuit of claim 8 , further comprising:
logic circuitry to provide a variable control voltage to a control terminal of the transistor.

14. The integrated circuit of claim 13 , wherein the switching circuitry is to provide, to the logic circuitry, the first variable voltage level in response to the first variable voltage level exceeding the second variable voltage level.

15. The integrated circuit of claim 13 , wherein the logic circuitry is to apply the first variable voltage level to the control terminal of the transistor when the first variable voltage level is exceeding the second variable voltage level.

16. A method of operating an integrated circuit, comprising:
receiving, by the integrated circuit, a first voltage level from an output driver power supply;
providing the first voltage level to a source terminal of a p-channel field effect transistor (PFET), the PFET having a drain terminal DC connected to a first external terminal of the integrated circuit, the first external terminal of the integrated circuit having a first variable pad voltage level that does not exceed the first voltage level while the integrated circuit is in an operational mode;
receiving, by the integrated circuit and while the integrated circuit is in a non-operational mode, a second voltage level from the output driver power supply, the second voltage level being less than the first voltage level;
receiving, by the integrated circuit and while the integrated circuit is in the non-operational mode, a second variable pad voltage level that is greater than the second voltage level; and
in response to the second variable pad voltage level being greater than the second voltage level, providing the second variable pad voltage level to a body terminal of the PFET.

17. The method of claim 16 , further comprising:
in response to the second variable pad voltage level being greater than the second voltage level, providing the second variable pad voltage level to a gate terminal of the PFET.

18. The method of claim 16 , further comprising:
in response to the second variable pad voltage level being greater than the second voltage level, controlling an NFET to be non-conducting.

19. The method of claim 16 , further comprising:
in response to the second variable pad voltage level being greater than the second voltage level, providing the second variable pad voltage level to logic circuitry coupled to a control terminal of the PFET; and
providing, by the logic circuitry, the second variable pad voltage level to a control terminal of the PFET.

20. The method of claim 16 , further comprising:
comparing the second variable pad voltage level to the second voltage level to determine whether the second variable pad voltage level is greater than the second voltage level.

Assignees

• Rambus Inc

Inventors

• Wijetunga Panduka
• Kumar Dhiraj

Classifications

• H03K19/007 Primary

  Fail-safe circuits · CPC title

• H03K19/00361 Primary

  in field effect transistor circuits · CPC title

• H03K19/00384

  in field effect transistor circuits · CPC title