Biased amplifier

Patent metadata

Field	Value
Publication number	US-11626848-B2
Application number	US-202117333395-A
Country	US
Kind code	B2
Filing date	May 28, 2021
Priority date	Oct 16, 2017
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

In one example an amplifier includes a bias circuit, an open-loop gain stage including a first PMOS having a gate coupled to a first node, a source coupled to a second node, a drain coupled to a third node, and a bulk coupled to the bias circuit, a second PMOS having a gate coupled to a ground node, a source coupled to the second node, a drain coupled to a fourth node, and a bulk coupled to the bias circuit, a first NMOS having a drain and a gate coupled to the third node and a source coupled to a fifth node, a second NMOS having a drain coupled to the fourth node, a gate coupled to the third node, and a source coupled to the fifth node, an adjustable resistor coupleable between the third and fourth nodes, and a buffer stage coupled to the open-loop gain stage.

First claim

What is claimed is:

1. An amplifier, comprising:
a bias circuit;
a compensation circuit;
a first p-type metal oxide semiconductor field effect transistor (MOSFET) (PMOS) having a source terminal coupled to a first node, a gate terminal coupled to a second node, a drain terminal coupled to a fourth node, and a bulk connection coupled to the bias circuit;
a second PMOS having a source terminal coupled to the first node, a gate terminal coupled to a third node, a drain terminal coupled to the compensation circuit at a fifth node, and a bulk connection coupled to the bias circuit;
a first n-type MOSFET (NMOS) having a drain terminal coupled to the fourth node and a gate terminal coupled to a sixth node; and
a second NMOS having a drain terminal coupled to a source terminal of the first NMOS, a gate terminal coupled to the fourth node, and a source terminal coupled to a seventh node.

2. The amplifier of claim 1 , wherein the bias circuit is configured to couple to a first resistor between an eighth node and a ninth node and a second resistor between the ninth node and the seventh node, wherein the eighth node is coupled to the bulk connection of the second PMOS, and wherein the ninth node is coupled to the bulk connection of the first PMOS.

3. The amplifier of claim 2 , wherein a voltage potential at the eighth node is greater than a voltage potential at the seventh node.

4. The amplifier of claim 1 , wherein the compensation circuit comprises:
a third NMOS having a gate terminal coupled to the sixth node, a drain terminal coupled to the fifth node, and a source terminal coupled to a tenth node;
a fourth NMOS having a gate terminal coupled to the fourth node, a drain terminal coupled to the tenth node, and a source terminal coupled to the seventh node;
a fifth NMOS having a gate terminal coupled to the fifth node, a drain terminal coupled to an eleventh node, and a source terminal coupled to the seventh node; and
a capacitor coupled between the tenth node and the eleventh node.

5. The amplifier of claim 4 , configured to couple to a third resistor between the eleventh node and the second node and a fourth resistor between the second node and the seventh node.

6. A circuit comprising:
an input configured to couple to a sensor;
an output;
a ground input;
a first resistor and a second resistor coupled in series between the output and the ground input;
a first transistor that includes a source, a drain, a gate, and a bulk, wherein the first resistor is coupled between the output and the gate of the first transistor;
a second transistor that includes a source, a drain, a gate, and a bulk, wherein the input is coupled to the gate of the second transistor;
a third resistor and a fourth resistor coupled in series between the source of the first transistor and the source of the second transistor; and
a bias circuit coupled to the bulk of the first transistor and to the bulk of the second transistor and configured to provide a first bias voltage at the bulk of the first transistor and a second bias voltage at the bulk of the second transistor.

7. The circuit of claim 6 further comprising:
a supply voltage input; and
a third transistor and a fourth transistor coupled in series between the supply voltage input and a first node, wherein the bias circuit is coupled between the first node and the ground input.

8. The circuit of claim 7 , wherein:
the bulk of the second transistor is coupled to the first node;
the bias circuit includes:
a fifth resistor coupled between the first node and a second node; and
a sixth resistor coupled between the second node and the ground input; and
the bulk of the first transistor is coupled to the second node.

9. The circuit of claim 7 further comprising a fifth transistor and a sixth transistor coupled in series between the supply voltage input and a second node that is between the third resistor and the fourth resistor.

10. The circuit of claim 9 , wherein:
a gate of the third transistor is coupled to a gate of the fifth transistor; and
a gate of the fourth transistor is coupled to a gate of the sixth transistor.

11. The circuit of claim 7 further comprising a seventh transistor and an eighth transistor coupled in series between the supply voltage input and the output.

12. The circuit of claim 11 , wherein:
a gate of the third transistor is coupled to a gate of a fifth transistor and a gate of the seventh transistor; and
a gate of the fourth transistor is coupled to a gate of a sixth transistor and a gate of the eighth transistor.

13. The circuit of claim 6 further comprising a compensation circuit coupled between the output and the ground input.

14. The circuit of claim 13 , wherein the compensation circuit includes:
a third transistor that includes a source coupled to the ground input, a drain coupled to the output, and a gate coupled to the second transistor;
a fourth transistor and a fifth transistor coupled in series between the second transistor and the ground input; and
a capacitor coupled between the output and a first node that is between the fourth transistor and the fifth transistor.

15. The circuit of claim 14 , further comprising a sixth transistor and a seventh transistor coupled in series between the first transistor and the ground input.

16. The circuit of claim 15 , wherein:
the sixth transistor includes a source, a drain coupled to the drain of the first transistor, and a gate coupled to a gate of the fourth transistor; and
the seventh transistor includes a source coupled to the ground input, a drain coupled to the source of the sixth transistor, and a gate coupled to a gate of the fifth transistor.

17. The circuit of claim 16 , wherein the gate of the fifth transistor and the gate of the seventh transistor are coupled to the drain of the first transistor.

18. A circuit comprising:
a positive supply voltage input;
a negative supply voltage input;
a first bias voltage input;
a second bias voltage input;
a sensor input;
an output;
a first transistor and a second transistor coupled in series between the positive supply voltage input and the output, wherein the first transistor includes a gate coupled to the first bias voltage input and the second transistor includes a gate coupled to the second bias voltage input;
a first resistor and a second resistor coupled in series between the output and the negative supply voltage input;
a third transistor coupled between the output and the negative supply voltage input;
a fourth transistor and a fifth transistor coupled in series between the positive supply voltage input and a first node, wherein the fourth transistor includes a gate coupled to the first bias voltage input and the fifth transistor includes a gate coupled to the second bias voltage input;
a third resistor, a sixth transistor, a seventh transistor, and an eighth transistor coupled in series between the first node and the negative supply voltage input, wherein the sixth transistor includes a gate coupled to a second node between the first resistor and the second resistor; and
a fourth resistor, a ninth transistor, a tenth transistor, and an eleventh transistor coupled in series between the first node and the negative supply voltage input, wherein the ninth transistor includes a gate coupled to the sensor input.

19. The circuit of claim 18 , wherein:
a gate of the seventh transistor is coupled to a gate of the tenth transistor;
a gate of the eighth transistor is coupled to a gate of the eleventh transistor; and
the circuit fu

Assignees

• Texas Instruments Inc

Inventors

• Prasad Sudheer

Classifications

• H03F2203/45342

  the AAC comprising control means on a back gate of the AAC · CPC title

• H03F3/45502 Primary

  Controlling the common emitter circuit of the differential amplifier · CPC title

• H03F3/45085 Primary

  Long tailed pairs (H03F3/45112, H03F3/45139 take precedence) · CPC title

• H03F3/45264

  Complementary cross coupled types · CPC title

• H03F3/45165

  Complementary cross coupled types · CPC title