Low noise amplifier for MEMS capacitive transducers

Patent metadata

Field	Value
Publication number	US-9729114-B2
Application number	US-201514700666-A
Country	US
Kind code	B2
Filing date	Apr 30, 2015
Priority date	May 2, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

This application relates to amplifier circuitry for amplifying a signal from a MEMS transducer. A super source follower circuit ( 40 ) is provided which includes a feedback path from its output node (N out ) to a control bias node (BC) in order to provide a preamplifier signal gain that may be greater than unity. A first transistor (M 1 ) is configured to have its gate node connected to an input node (N IN ) for receiving the input signal (V IN ) and its drain node connected to an input node (X) of an output stage (A). The source node of the first transistor is connected to the output node (N OUT ). A current source (I 2 ) is configured to deliver a current to the drain node of the first transistor (M 1 ), wherein the current source (I 2 ) is controlled by a bias control voltage (V BC ) at the bias control node (BC). A feedback impedance network (Z 1 ) comprising a first port connected to the output node (N OUT ) and a second port connected to the bias control node (BC) is provided.

First claim

The invention claimed is:

1. An amplifier circuit for receiving an input signal from a MEMS transducer at an input node, and delivering an amplified output signal at an output node, the amplifier circuit comprising:
an output stage with an output connected to the output node;
an input stage comprising,
a first transistor, having its gate node connected to said input node, its source node connected to said output node and its drain node connected to an input of said output stage;
a current source configured to deliver a current to the drain node of said first transistor, wherein said current source is controlled by a bias control voltage at a bias control node; and
a feedback impedance network comprising:
a first port connected to the output node and a second port connected to the bias control node; and
at least a first capacitor between the first port and the second port.

2. An amplifier circuit for receiving an input signal from a MEMS transducer at an input node, and delivering an amplified output signal at an output node, the amplifier circuit comprising:
an output stage with an output connected to the output node;
an input stage comprising,
a first transistor, having its gate node connected to said input node, its source node connected to said output node and its drain node connected to an input of said output stage;
a current source configured to deliver a current to the drain node of said first transistor, wherein said current source is controlled by a bias control voltage at a bias control node; and
a feedback impedance network comprising:
a first port connected to the output node and a second port connected to the bias control node; and
a third port connected to a reference voltage such that the feedback impedance network forms a potential divider with the second port delivering an attenuated version of the output signal.

3. An amplifier circuit as claimed in claim 2 , wherein the feedback impedance network comprises at least a second capacitor between the second port and the third port.

4. An amplifier circuit as claimed in claim 2 , wherein the potential divider is configured as a variable potential divider.

5. An amplifier circuit as claimed in claim 1 , wherein the feedback impedance network comprises at least one capacitor and at least one resistor.

6. An amplifier circuit as claimed in claim 1 , wherein the feedback impedance network comprises an adjustable capacitance.

7. An amplifier circuit as claimed in claim 1 , wherein the feedback impedance network comprises a plurality of capacitive components and a network of switches, said network of switches being configured for selectively connecting one or more of said plurality of capacitive components to the second port.

8. An amplifier circuit as in claim 1 , wherein the feedback impedance network comprises a plurality of capacitive components and a network of switches, said network of switches being configured for selectively connecting one or more of said plurality of capacitive components to the first port or the third port.

9. An amplifier circuit as claimed in claim 1 , wherein the bias control node is connected to a bias voltage via a high impedance structure.

10. An amplifier circuit as claimed in claim 9 , further comprising a switch across the high impedance structure.

11. An amplifier circuit as claimed in claim 1 , wherein the current source is a second transistor with its drain node connected to the drain node of the first transistor, its gate node connected to the bias control node, and its source node connected to a reference voltage.

12. An amplifier circuit as claimed in claim 1 , wherein the current source is a second transistor with its drain node connected to the drain node of the first transistor, its body node connected to the bias control node, and its source node connected to a reference voltage.

13. An amplifier circuit as claimed in claim 1 , wherein the output stage comprises a third transistor with its drain node connected to the output node, its source node connected to a reference voltage, and its gate node connected to the input node of the output stage.

14. An amplifier circuit as claimed in claim 1 , comprising a circuit element coupled between a supply voltage and the output node, wherein the circuit element comprises a fourth transistor configured as a constant current source.

15. An amplifier circuit as claimed in claim 14 , wherein the drain node of the fourth transistor is connected to the output node, the source node of the fourth transistor is connected to the supply voltage, and the gate node of the fourth transistor is coupled to the input node of the output stage to provide a Class AB output configuration.

16. An amplifier circuit as claimed in claim 15 , wherein the drain of the fourth transistor is connected to the output node, the source node is connected to the supply voltage, and the gate node is coupled to a fifth transistor.

17. An amplifier circuit as claimed in claim 16 , wherein the gate and drain nodes of the fifth transistor are coupled to the input of the inverting output gain stage to vary the dependence of the fourth transistor on the voltage at said input of the output stage.

18. An integrated circuit comprising an amplifier circuit as claimed in claim 1 , wherein said MEMS transducer is formed on a monolithic substrate with said integrated circuit.

19. An amplifier circuit as claimed in claim 1 , comprising a MEMS transducer coupled to said input node wherein said MEMS transducer is a MEMS microphone.

20. An electronic device comprising an amplifier circuit as claimed in claim 1 , wherein said device comprises at least one of: a portable device; a battery powered device; a computing device; a communications device; an audio device; a personal media player; a games device; a mobile telephone; a laptop computer and a tablet computing device.

Assignees

• Cirrus Logic Int Semiconductor Ltd

Inventors

• Astgimath Santosh

Classifications

• H03F3/187 Primary

  in integrated circuits · CPC title

• H03F3/183

  with semiconductor devices only · CPC title

• H04R19/005

  using semiconductor materials · CPC title

• H03G1/0094

  using switched capacitors · CPC title

• H03F1/26

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title