Read-out for MEMS capacitive transducers

Patent metadata

Field	Value
Publication number	US-9287834-B2
Application number	US-201414448848-A
Country	US
Kind code	B2
Filing date	Jul 31, 2014
Priority date	Aug 2, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

Amplifier arrangements for read-out of MEMS capacitive transducers, such as low-noise amplifiers. An amplifier circuit has first and second MOS transistors, with the gate of the first transistor driven by the input signal, and the gate of the second transistor driven by a reference. The sources of the first and second transistors are connected via an impedance. Modulation circuitry is arranged to monitor a signal with a value that varies with the input signal and to modulate the back-bias voltage between the bulk and source terminals of the first and second transistors with the applied modulation being equal for each transistor and based on said monitored signal. The back-bias of the first transistor can be increase to extend the input range of the transistor in situations where the input signal may otherwise result in signal clipping, while avoiding noise and power issues for other input signal levels. By applying an equal modulation to the back-bias of each transistor, there is no substantial modulation of the output signal.

First claim

What is claimed is:

1. An amplifier circuit for amplifying an input signal from a MEMS capacitive transducer, the circuit comprising:
first and second MOS transistors each having source, gate, drain and bulk terminals, wherein the gate terminal of the first transistor is configured to receive the input signal and the source terminal of the first transistor is electrically coupled to the source terminal of the second transistor via an impedance and the gate terminal of the second transistor is configured to receive a reference voltage; and
modulation circuitry configured to:
receive a monitored signal which has a value that varies with the value of the input signal relative to said reference voltage; and
controllably modulate a back-bias voltage between the bulk terminal and the source terminal of the first transistor and also a back-bias voltage between the bulk terminal and the source terminal of the second transistor,
wherein the modulation applied to vary the back-bias voltage of each transistor is equal and based on said monitored signal.

2. An amplifier circuit as claimed in claim 1 wherein said modulation circuitry is configured to modulate the back-bias voltages of the first and second transistors so that the back-bias voltages are greater for a first range of values of the monitored signal relative to a second range of values of the monitored signal.

3. An amplifier circuit as claimed in claim 2 wherein for said second range of values said modulation circuitry is configured to apply a zero value modulation to said back-bias voltages.

4. An amplifier circuit as claimed in claim 1 wherein the modulation circuitry is configured to:
maintain the voltage of the bulk terminal of each of said transistors so as to maintain the back-bias voltages of the transistors at base values if the monitored signal does not exceed a first boundary; and
modulate the voltage of the bulk terminal of said each of said transistors so as to increase the back-bias voltages if the monitored signal exceeds the first boundary.

5. An amplifier circuit as claimed in claim 4 wherein said first boundary is set so as to correspond to the edge of a saturation operating mode of the first transistor in use with the first transistor having a back-bias voltage at the base value.

6. An amplifier circuit as claimed in claim 4 wherein said first boundary is set such that, when the monitored signal is at the first boundary, the value of the input signal is within a range of 50-150 mV of the edge of a saturation operating mode with the first transistor having a back-bias voltage at the base value.

7. An amplifier circuit as claimed in claim 4 wherein said first boundary is set such that, when the monitored signal is at the first boundary the value of the input signal is within a range of about −400 mv to −250 mV.

8. An amplifier as claimed in claim 4 wherein the base value of back-bias for the first transistor is substantially zero.

9. An amplifier circuit as claimed in claim 4 wherein the modulation circuitry is configured such that, when the monitored signal exceeds the first boundary, the magnitude of the back-bias voltage modulation applied increases with magnitude of the monitored signal.

10. An amplifier circuit as claimed in claim 9 wherein the magnitude of the back-bias voltage modulation applied increases with magnitude of the monitored signal until a maximum voltage modulation is reached.

11. An amplifier circuit as claimed in claim 1 wherein for at least some values of the monitored signal the back-bias voltage modulation is increased so as to allow an input signal peak value of at least −800 mV to be amplified without substantial clipping.

12. An amplifier circuit as claimed in claim 1 wherein the modulation circuitry comprises control circuitry for determining the amount of any voltage modulation to be applied and adjustment circuitry, responsive to the control circuitry, to apply any modulation.

13. An amplifier circuit as claimed in claim 12 wherein, for each said first and second transistors the bulk terminal and source terminal of the transistor are connected via a resistance and wherein the adjustment circuitry comprises first and second current sources for generating respective modulation currents at the bulk terminals of the first and second transistors in response to the control circuitry.

14. An amplifier circuit as claimed in claim 13 wherein said first and second current sources are current mirrors configured to replicate a control current generated by said control circuitry.

15. An amplifier circuit as claimed in claim 13 further comprising first and second current sinks respectively connected to the source terminals of the first and second transistors for sinking a current substantially equal to the respective modulation current.

16. An amplifier circuit as claimed in claim 12 wherein the control circuitry comprises a control differential amplifier for receiving the monitored signal and generating a control current based on the monitored signal.

17. An amplifier circuit as claimed in claim 16 wherein said control differential amplifier has an input voltage offset such that the control current is zero unless the monitored signal exceeds the input voltage offset.

18. An amplifier circuit as claimed in claim 17 wherein said control differential amplifier comprises first and second control circuit transistors and said first and second control circuit transistors have different channel characteristics to provide at least part of said input voltage offset.

19. An amplifier circuit as claimed in claim 17 wherein said control differential amplifier comprises first and second control circuit transistors and said first and second control circuit transistors are configured to have different source voltages and/or currents in use so as to provide at least part of said input voltage offset.

20. An amplifier circuit as claimed in claim 16 wherein said control differential amplifier generates an intermediate current and the control circuit further comprises at least one current source or current sink for generating a threshold current configured such that the control current corresponds to any component of the intermediate current greater than the threshold current.

21. An amplifier circuit as claimed in claim 1 wherein the first and second transistors are configured as part of a differential amplifier to generate a differential signal corresponding to the input signal.

22. An amplifier circuit as claimed in claim 21 wherein said differential signal is used as said monitored signal.

23. An amplifier circuit as claimed in claim 21 further comprising common-mode control circuitry for controlling the common-mode voltage of said differential signal.

24. An amplifier circuit as claimed in claim 23 wherein said common-mode control circuitry comprises comparison circuitry for comparing a drain voltage of each of the first transistor and second transistor with a reference bias voltage and adjusting source currents supplied to the source terminals of each of the first transistor and second transistor.

25. An amplifier circuit as claimed in claim 1 wherein said first and second transistors are P-channel MOS transistors and increasing the back-bias voltage of said transistors comprises modulating the voltage of the bulk terminal to be more positive than the voltage of the source terminal.

26. An amplifier circuit as c

Assignees

• Cirrus Logic Internat Uk Ltd
• Cirrus Logic Int Semiconductor Ltd

Inventors

• Lasseuguette Jean Pierre
• Deas James

Classifications

• H03F1/0266

  by using a signal derived from the input signal · CPC title

• H04R3/00

  Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title

• H03F2003/45008

  Electricity · mapped topic

• H03F2203/45498

  the CSC comprising only resistors · CPC title

• H03F2203/45396

  the AAC comprising one or more switches · CPC title