Efficient fabrication of memory structures

Patent metadata

Field	Value
Publication number	US-11626452-B2
Application number	US-202016940774-A
Country	US
Kind code	B2
Filing date	Jul 28, 2020
Priority date	Jul 28, 2020
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.

First claim

What is claimed is:

1. A method, comprising:
depositing a first metal material over a substrate to form a first metal layer corresponding to a first access line associated with accessing a first memory cell;
depositing at least a first cell material over the first metal layer to form a cell layer comprising the first memory cell;
depositing, using a single deposition process, a second metal material over the cell layer to form a second metal layer corresponding to a second access line associated with accessing the first memory cell;
depositing a first mask material over the second metal material to form a first mask layer;
performing a first etching process to remove a first portion of the first mask layer, a first portion of the second metal layer, and a first portion of the first cell material; and
forming a second memory cell over a remaining portion of the second metal layer, wherein the second access line is further associated with accessing the second memory cell.

2. The method of claim 1 , wherein depositing the at least the first cell material comprises:
depositing a first electrode material over the first metal layer to form a first electrode layer;
depositing a cell storage material over the first electrode layer to form a cell storage layer; and
depositing a second electrode material over the cell storage layer to form a second electrode layer, wherein the cell layer comprises the first electrode layer, the cell storage layer, and the second electrode layer.

3. The method of claim 2 , wherein the first electrode material comprises a conductive carbon material and the second electrode material comprises the conductive carbon material.

4. The method of claim 2 , wherein the cell storage material comprises a chalcogenide material.

5. The method of claim 2 , wherein performing the first etching process further comprises:
performing the first etching process before forming the second memory cell to remove a first portion of the first electrode layer, a first portion of the cell storage layer, and a first portion of the second electrode layer,
wherein the first memory cell comprises a second portion of the first electrode layer, a second portion of the cell storage layer, and a second portion of the second electrode layer.

6. The method of claim 5 , further comprising:
depositing, after performing the first etching process, a sealing material over a surface of a first stack comprising a remaining portion of the first mask layer, the remaining portion of the second metal layer, and the first memory cell; and
performing a removal procedure to remove a first portion of the sealing material and the remaining portion of the first mask layer to expose a surface of the remaining portion of the second metal layer, wherein forming the second memory cell over the second metal layer comprises forming the second memory cell over the surface of the remaining portion of the second metal layer.

7. The method of claim 6 , further comprising:
depositing a dielectric material over the sealing material before performing the removal procedure, wherein performing the removal procedure further comprises removing a first portion of the dielectric material.

8. The method of claim 7 , wherein:
performing the removal procedure comprises performing a planarization process to generate a planar surface comprising the surface of the remaining portion of the second metal layer and a surface of a remaining portion of the dielectric material.

9. The method of claim 8 , wherein forming the second memory cell comprises:
depositing the first electrode material over the planar surface to form a third electrode layer;
depositing the cell storage material over the third electrode layer to form a second cell storage layer;
depositing the second electrode material over the second cell storage layer to form the second electrode layer;
depositing the first mask material over the second electrode layer to form a second mask layer; and
performing a second etching process to remove a first portion of the second mask layer, a first portion of the third electrode layer, a first portion of the second cell storage layer, and a first portion of a fourth electrode layer, wherein the second memory cell comprises a remaining portion of the third electrode layer, a remaining portion of the second cell storage layer, and a remaining portion of the fourth electrode layer.

10. The method of claim 9 , further comprising:
depositing, after performing the second etching process, a second sealing material over a surface of a second stack comprising a remaining portion of the second mask layer and the second memory cell;
depositing a second dielectric material over the second sealing material; and
performing a second removal procedure to remove a first portion of the second sealing material, the remaining portion of the second mask layer, and a first portion of the second dielectric material to expose a second surface.

11. The method of claim 10 , further comprising:
depositing a third metal material over the second surface to form a third metal layer corresponding to a third access line associated with accessing the second memory cell.

12. The method of claim 1 , wherein the second metal layer comprises a quantity of the second metal material deposited using the single deposition process and excludes any additional quantity of the second metal material deposited as part of another deposition process.

13. The method of claim 1 , wherein the first metal material and the second metal material comprise tungsten.

Assignees

• Micron Technology Inc

Inventors

• Lee Don Koun
• Baker Kevin Lee
• Wei Lei

Classifications

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• H10N70/882

  Compounds of sulfur, selenium or tellurium, e.g. chalcogenides · CPC title

• H10B63/84 Primary

  arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays · CPC title

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title