Memory arrays and methods used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-11626423-B2
Application number	US-202117373278-A
Country	US
Kind code	B2
Filing date	Jul 12, 2021
Priority date	Aug 20, 2019
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a lower stack comprising vertically-alternating lower insulative tiers and lower conductive tiers, the lower stack comprising lower-laterally-spaced memory-block regions;
forming lower-elevationally-extending holes in the lower stack that are laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent lower-memory-block regions;
forming sacrificial material in the lower holes;
forming an upper stack comprising vertically-alternating upper insulative tiers and upper conductive tiers above the lower stack and the sacrificial material, the upper stack comprising upper-laterally-spaced memory-block regions that are directly above the lower-memory-block regions;
forming upper-elevationally-extending holes in the upper stack that are laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent upper-memory-block regions, the upper holes being atop and exposing the sacrificial material in the lower holes, insulative material of the respective lower insulative tiers and the upper insulative tiers extending around the respective upper and lower holes and laterally across space that is laterally-between the immediately-laterally-adjacent lower-memory-block regions and the immediately-laterally-adjacent upper-memory-block regions; and
removing the sacrificial material through the upper holes.

2. The method of claim 1 comprising forming channel openings into the lower and upper stacks, the upper and lower holes being formed to be everywhere larger in horizontal cross-section than the channel openings.

3. The method of claim 1 comprising filling the upper and lower holes with insulative material after the removing.

4. The method of claim 1 comprising, after the removing and through the upper and lower holes, isotropically etching away and replacing placeholder material that is in the upper and lower conductive tiers with conducting material of individual conductive lines.

5. The method of claim 4 comprising:
filling the upper and lower holes with insulative material after the removing; and
laterally recessing the conducting material relative to the upper and lower holes prior to said filling.

6. The method of claim 1 comprising forming individual memory cells of the strings of memory cells to comprise channel material of operative channel-material strings, a gate region that is part of a conductive line in individual of the upper and lower conductive tiers, and a memory structure laterally-between the gate region and the channel material of the operative channel-material strings in the individual upper and lower conductive tiers, conducting material of the upper and lower conductive tiers being formed after the removing.

7. The method of claim 1 comprising forming individual memory cells of the strings of memory cells to comprise channel material of operative channel-material strings, a gate region that is part of a conductive line in individual of the upper and lower conductive tiers, and a memory structure laterally-between the gate region and the channel material of the operative channel-material strings in the individual upper and lower conductive tiers, conducting material of the upper and lower conductive tiers being formed before forming the upper and lower holes.

8. The method of claim 1 comprising forming the upper and lower holes to be vertical or within 10° of vertical.

Assignees

• Micron Technology Inc

Inventors

• Zhang Xiaosong
• Hu Yi
• John Tom J
• Ng Wei Yeeng
• Tiwari Chandra

Classifications

• H10P50/283

  by chemical means · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title