Semiconductor devices having buried gates

Patent metadata

Field	Value
Publication number	US-11626409-B2
Application number	US-202117318563-A
Country	US
Kind code	B2
Filing date	May 12, 2021
Priority date	Sep 8, 2020
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including an active region;
a gate structure extending primarily in a first direction in a gate trench in the substrate;
a bit line extending primarily in a second direction, intersecting the first direction, on the substrate, the bit line being electrically connected to the active region on a first side of the gate structure; and
a capacitor disposed on the bit line, and electrically connected to the active region on a second side of the gate structure,
wherein the gate structure comprises:
a gate dielectric layer disposed on a bottom surface and inner side surfaces of the gate trench;
a first conductive layer disposed on the gate dielectric layer, in a lower portion of the gate trench;
sidewall insulating layers disposed on the gate dielectric layer and on an upper surface of the first conductive layer;
a second conductive layer disposed on the first conductive layer and including graphene; and
a buried insulating layer at least partially filling a space between the sidewall insulating layers, on the second conductive layer.

2. The semiconductor device of claim 1 , wherein the first conductive layer has a first length, and the second conductive layer has a second length that is longer than the first length in a direction perpendicular to an upper surface of the substrate.

3. The semiconductor device of claim 1 , wherein the gate dielectric layer has a first thickness, and each of the sidewall insulating layers has a second thickness that is lower than the first thickness.

4. The semiconductor device of claim 1 , wherein the second conductive layer has a thickness in a range of about 6 Å to about 50 Å.

5. The semiconductor device of claim 1 , wherein the second conductive layer is at least partially surrounded by the first conductive layer, the sidewall insulating layers, and the buried insulating layer.

6. The semiconductor device of claim 1 , wherein the second conductive layer is disposed on the sidewall insulating layers on the first conductive layer, and
wherein the gate structure further comprises a third conductive layer at least partially filling a space within the second conductive layer on the first conductive layer.

7. The semiconductor device of claim 6 , wherein the second conductive layer is at least partially surrounded by the first conductive layer, the sidewall insulating layers, the third conductive layer, and the buried insulating layer.

8. The semiconductor device of claim 1 , wherein the gate structure further comprises a third conductive layer disposed on the sidewall insulating layers on the first conductive layer, and
wherein the second conductive layer at least partially fills a space within the third conductive layer on the first conductive layer.

9. The semiconductor device of claim 8 , wherein the second conductive layer is at least partially surrounded by the third conductive layer and the buried insulating layer.

10. The semiconductor device of claim 1 , wherein the first conductive layer comprises a first layer in contact with the gate dielectric layer and a second layer at least partially filling a space within the first layer, and wherein the second layer comprises a material having a resistivity that is lower than a resistivity of the first layer.

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronis Co Ltd

Inventors

• Kim Huijung
• Kwon Minwoo
• Han Sangyeon
• Kim Sangwon
• Kim Junsoo
• Shin Hyeonjin
• Lee Eunkyu

Classifications

• H10D64/01304

  characterised by the conductor · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D30/668

  having trench gate electrodes, e.g. UMOS transistors · CPC title

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title