DRAM with selective epitaxial cell transistor

Patent metadata

Field	Value
Publication number	US-11626407-B2
Application number	US-202217687707-A
Country	US
Kind code	B2
Filing date	Mar 7, 2022
Priority date	Jan 28, 2020
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly doped diffusion region. A semiconductor pillar is then formed in the opening by selective epitaxial growth. An end of the semiconductor pillar is then doped and the doped end is connected with a memory element.

First claim

The invention claimed is:

1. A method for manufacturing a dynamic random access memory device, the method comprising:
providing a semiconductor substrate;
forming a highly doped diffusion region in a surface of the semiconductor substrate;
depositing a wordline structure on the surface of the semiconductor substrate, the wordline structure including an electrically conductive gate layer;
forming an opening in the wordline structure, the opening being located at a first end of and extending to the highly doped diffusion region;
forming a semiconductor pillar in the opening by selective epitaxial growth;
doping an end of the semiconductor pillar; and
connecting the semiconductor pillar with a memory element.

2. The method according to claim 1 , wherein forming a highly doped diffusion region in a surface of the semiconductor substrate comprises:
forming a mask structure over the semiconductor substrate, the mask being configured to cover areas of the substrate wherein highly doped diffusion regions are to be formed;
performing an etching process to remove portions of the substrate not protected by the mask, leaving trenches surrounding the mask;
filling the trenches with an insulating fill material;
removing the mask and planarizing a surface of the substrate including the formed insulating fill material; and
doping exposed portions of the semiconductor substrate not filled with the insulating fill material.

3. The method according to claim 1 , further comprising, after forming the opening and before forming the semiconductor pillar, forming a gate dielectric layer on an inner side of the opening.

4. The method according to claim 3 , further comprising, after forming the gate dielectric layer and before forming the semiconductor pillar, removing the gate dielectric layer horizontally from a bottom of the opening to expose the underlying highly doped diffusion region, leaving the gate dielectric layer remaining only on inner sides of the opening.

5. The method according to claim 4 , further comprising: performing an etching process to remove residue from the bottom of the opening, leaving only highly doped semiconductor material exposed at the opening.

6. The method according to claim 5 , wherein the etching process forms a beveled surface of the highly doped semiconductor material exposed at the opening.

7. The method according to claim 6 , wherein the semiconductor pillar formed in the opening by the selective epitaxial growth has at least 80 percent monocrystalline by volume.

8. The method according to claim 6 , wherein the semiconductor pillar formed in the opening by the selective epitaxial growth has at least 90 percent monocrystalline by volume.

9. The method according to claim 1 , further comprising forming a wordline structure by:
forming a mask over a semiconductor pillar and wordline structure, wherein the mask is configured to define one or more parallel wordlines;
performing an etching process to remove portions of the wordline structure that are not protected by the mask; and
removing the mask, leaving the one or more parallel wordlines.

10. The method according to claim 9 , wherein a formed wordline is at a diagonal relative to the highly doped diffusion region.

11. The method according to claim 9 , further comprising: depositing a dielectric fill layer to fill areas between the parallel wordlines.

12. The method according to claim 11 , further comprising forming a bitline structure by:
performing a masking and etching process to form an opening in the dielectric fill material, the formed opening extending to the highly doped diffusion region; and
depositing an electrically conductive material into the opening formed in the dielectric fill material to form an electrically conductive conduct, to provide electronic contact between the highly doped diffusion region and bitline circuitry.

13. The method according to claim 1 , further comprising, after doping the end of the semiconductor pillar and before connecting the semiconductor pillar with the memory element, forming an electrical contact over and electrically connected with the semiconductor pillar.

14. The method according to claim 1 , wherein the memory element is a capacitor.

15. The method according to claim 1 , wherein the memory element is a Dynamic Random Access Memory (DRAM).

16. The method according to claim 1 , wherein the wordline structure further comprises first and second dielectric layers arranged such that the electrically conductive gate layer is located between the first and second dielectric layers.

17. The method according to claim 1 , wherein the semiconductor pillar comprises silicon.

18. The method according to claim 1 , wherein the semiconductor pillar comprises silicon-germanium.

19. The method according to claim 1 , wherein the semiconductor pillar comprises indium-gallium-arsenide.

Assignees

• Integrated Silicon Solution Cayman Inc

Inventors

• Walker Andrew J
• Beery Dafna
• Cuevas Peter
• Levi Amitay

Classifications

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title