Method for manufacturing magnetic memory element with post pillar formation annealing

Patent metadata

Field	Value
Publication number	US-10916696-B2
Application number	US-201916400204-A
Country	US
Kind code	B2
Filing date	May 1, 2019
Priority date	May 1, 2019
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A method for manufacturing a magnetic memory element structure using a Ru hard mask and a post pillar thermal annealing process. A Ru hard mask is formed over a plurality of memory element layers and an ion milling is performed to transfer the image of the Ru hard mask onto the underlying memory element layers. A high-angle ion milling an be performed to remove any redeposited material from the sides of the memory element layers, and a non-magnetic, dielectric material can be deposited. A thermal annealing process can then be performed to repair any damage caused by the previously performed ion milling processes.

First claim

What is claimed is:

1. A method for manufacturing a magnetic memory element, comprising:
depositing a plurality of memory element layers over a substrate;
depositing a layer of Ru;
forming a mask structure over the layer of Ru;
transferring the image of the mask structure onto the layer of Ru to form a Ru hard mask;
performing an ion milling to transfer the image of the Ru hard mask layer onto the plurality of memory element layers to form a memory element pillar structure;
depositing a non-magnetic, dielectric isolation layer to surround the memory element pillar structure; and
performing a thermal annealing process after deposition of the non-magnetic, dielectric isolation layer;
wherein the plurality of memory element layers includes a non-magnetic, electrically insulating barrier layer as well as other layers, the method further comprising after performing the ion milling and before depositing the non-magnetic, dielectric isolation layer, performing a high angle ion milling to remove material redeposited on the side of the pillar structure during the ion milling process, and wherein the thermal annealing process repairs damage to the non-magnetic, electrically insulating barrier layer caused by the high angle ion milling and also recrystallizes the other layers of the plurality of magnetic memory element pillars.

2. The method as in claim 1 , wherein the thermal annealing comprises:
heating the plurality of memory element layers to a temperature of 350-450 degrees C.

3. The method as in claim 1 , wherein the thermal annealing comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. for a duration of 10-100 minutes.

4. The method as in claim 1 , wherein the thermal annealing comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. for a duration of 10-100 minutes in a vacuum annealing tool.

5. The method as in claim 1 , wherein the thermal annealing comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. for a duration of 10-100 minutes in a vacuum of at least 1×10 4 Torr.

6. The method as in claim 1 , wherein the thermal annealing comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. and cooling the plurality of memory element layers to room temperature.

7. A method for manufacturing a magnetic memory element, comprising:
depositing a plurality of memory element layers over a substrate, the plurality of memory element layers including a magnetic reference layer a non-magnetic barrier layer deposited over the magnetic reference layer and a magnetic free layer deposited over the non-magnetic barrier layer;
depositing Ru hard mask layer;
depositing a RIEable hard mask layer over the Ru hard mask layer;
forming a photoresist mask over the RIEable hard mask layer;
performing a reactive ion etching to transfer the image of the photoresist mask onto the RIEable hard mask layer;
performing an ion milling to transfer the image of the RIEable hard mask onto the Ru hard mask layer to form a patterned Ru hard mask, and continuing the ion milling to transfer the image of the patterned Ru hard mask onto at least a portion of the plurality of memory element layers;
depositing a non-magnetic, dielectric isolation layer to surround the memory element pillar structure; and
performing a thermal annealing process to repair any damage to the layers of the memory element pillar structure;
wherein the plurality of memory element layers includes a non-magnetic, electrically insulating barrier layer as well as other layers, the method further comprising after performing the ion milling and before depositing the non-magnetic, dielectric isolation layer, performing a high angle ion milling to remove material redeposited on the side of the pillar structure during the ion milling process, and wherein the thermal annealing process repairs damage to the non-magnetic, electrically insulating barrier layer caused by the high angle ion milling and also recrystallizes the other layers of the plurality of magnetic memory element pillars.

8. The method as in claim 7 , wherein the RIEable hard mask comprises one or more of silicon oxide, tantalum, tantalum nitride or diamond like carbon.

9. The method as in claim 7 , wherein the thermal annealing process includes heating the plurality of memory element layers to a temperature of 350-450 degrees C.

10. The method as in claim 7 , wherein the thermal annealing process comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. for a duration of 40-100 minutes.

11. The method as in claim 7 , wherein the thermal annealing process comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. for a duration of 40-100 minutes in a vacuum of at least 1×10 4 Torr.

12. The method as in claim 7 , wherein the thermal annealing process comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. and cooling the plurality of memory element layers back to room.

13. A method for manufacturing a magnetic memory element, comprising:
depositing a plurality of memory element layers including a magnetic reference layer, a non-magnetic barrier layer deposited over the magnetic reference layer and a magnetic free layer deposited over the non-magnetic barrier layer;
depositing a Ru layer over the plurality of memory element layers;
forming a mask structure over the Ru layer;
transferring the image of the mask structure onto the Ru layer to form a Ru hard mask;
performing a first ion milling to remove a portion of the plurality of memory element layers, the first ion milling being terminated when the magnetic reference layer has been reached;
depositing a non-magnetic, dielectric protective layer;
performing a second ion milling;
depositing a non-magnetic, dielectric isolation layer; and
performing a thermal annealing.

14. The method as in claim 13 , wherein the thermal annealing comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C.

15. The method as in claim 13 , wherein the thermal annealing comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. for a duration of 10 to 100 minutes.

16. The method as in claim 13 , wherein the thermal annealing comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. for a duration of 10-100 minutes in a vacuum of at least 1×10 −4 Torr.

17. The method as in claim 13 , wherein the thermal annealing comprises heating the plurality of memory element layers to a temperature of 350-450 degrees C. and cooling the plurality of memory element layers to room temperature in a vacuum of at least 1×10 −4 Torr.

18. The method as in claim 13 , further comprising after performing the ion milling and before depositing the non-magnetic, dielectric isolation layer, performing a high angle ion milling to remove material redeposited on the side of the pillar structure during the ion milling process.

Assignees

• Spin Memory Inc

Inventors

• Pinarbasi Mustafa
• Manandhar Pradeep
• Vasquez Jorge
• KARDASZ Bartlomiej Adam
• Boone Thomas D

Classifications

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H01L43/08

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic

• H01L27/224

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic