Etched facet in a multi quantum well structure

Patent metadata

Field	Value
Publication number	US-11624872-B2
Application number	US-202117539474-A
Country	US
Kind code	B2
Filing date	Dec 1, 2021
Priority date	Nov 21, 2018
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

An exemplary multi quantum well structure may include a silicon platform having a pit formed in the silicon platform, a chip positioned inside the pit, a first waveguide formed in the chip, and a second waveguide formed in the silicon platform. The pit may be defined at least in part by a sidewall and a base. The chip may include a first side and a first recess in the first side. The first side may be defined in part by a first cleaved or diced facet. The first recess may be defined in part by a first etched facet. The first waveguide may be configured to guide an optical beam to pass through the first etched facet. The second waveguide may be configured to guide the optical beam to pass through the sidewall. The second waveguide may be optically aligned with the first waveguide.

First claim

What is claimed is:

1. A method comprising:
providing a silicon platform, wherein a pit in the silicon platform is defined at least in part by a sidewall and a base;
bonding a chip within the pit, wherein the chip comprises a side defined in part by a cleaved or diced facet; and
etching a facet in the cleaved or diced facet of the chip to form an etched facet, defining a part of a recess in the side of the chip, after bonding the chip to the silicon platform; and
disposing a contact metal on the chip at a predetermined distance from the etched facet.

2. The method of claim 1 , further comprising etching the chip to form a first waveguide in the chip, after bonding the chip to the silicon platform, wherein the first waveguide is configured to guide an optical beam along an optical path to pass through the etched facet.

3. The method of claim 2 , wherein the first waveguide extends in a longitudinal direction that is substantially perpendicular to the sidewall.

4. The method of claim 2 , further comprising etching the silicon platform to form a second waveguide, wherein:
the second waveguide is formed in the silicon platform after bonding the chip to the silicon platform; and
the second waveguide is configured to guide the optical beam to pass through the sidewall.

5. The method of claim 4 , wherein:
the side is a first side;
the cleaved or diced facet is a first cleaved or diced facet;
the recess is a first recess;
the etched facet is a first etched facet;
the chip further comprises:
a second side defined in part by a second cleaved or diced facet; and
a second recess in the second side;

the second cleaved or diced facet is opposite to the first cleaved or diced facet;
the method further comprises etching a facet in the second cleaved or diced facet of the chip to form a second etched facet, defining a part of the second recess in the second side of the chip, after bonding the chip to the silicon platform; and
the first waveguide is configured to guide the optical beam to pass through the second etched facet.

6. The method of claim 5 , further comprising forming a third etched facet, a fourth etched facet, and a third waveguide extending from the third etched facet to the fourth etched facet, after bonding the chip to the silicon platform, wherein:
a distance between the first etched facet and the second etched facet defines a length of the first waveguide;
a distance between the third etched facet and the second etched facet defines a length of the third waveguide; and
the length of the first waveguide is longer than the length of the third waveguide.

7. The method of claim 5 , wherein the contact metal having a first end and a second end opposite to the first end, wherein:
the first end of the contact metal is substantially aligned with the first etched facet; and
the second end of the contact metal is substantially aligned with the second etched facet.

8. The method of claim 7 , wherein the contact metal is disposed directly on the chip.

9. The method of claim 7 , wherein the first end of the contact metal is disposed on the chip at a predetermined distance from the first etched facet, and the predetermined distance from the first end to the etched facet is equal to or less than 8000 nm.

10. The method of claim 1 , wherein the etched facet is positioned at a predetermined distance from the sidewall.

11. The method of claim 1 , wherein the etched facet is oriented at a predetermined angle relative to the sidewall.

12. The method of claim 1 , wherein the etched facet is skewed with respect to at least one of the sidewall or the cleaved or diced facet.

13. A method comprising:
bonding a chip to a platform, wherein the chip has a side defined by a cleaved or diced facet;
etching an etched facet to form a recess in the side, after bonding the chip to the platform, wherein the etched facet is positioned to intersect an optical path of light passing through the chip; and
disposing a contact metal on the chip at a predetermined distance from the etched facet.

14. The method of claim 13 , wherein the etched facet is substantially parallel to the cleaved or diced facet.

15. The method of claim 13 , wherein the etched facet is skewed relative to the cleaved or diced facet.

16. The method of claim 13 , wherein the contact metal including an end that is substantially aligned with the etched facet.

17. The method of claim 16 , wherein the side is a first side, the cleaved or diced facet is a first cleaved or diced facet, the recess is a first recess, the etched facet is a first etched facet, a second side is defined in part by a second cleaved or diced facet opposite to the first cleaved or diced facet, the method further comprising:
etching a second etched facet to form a second recess in the second side; and
positioning the second etch facet to intersect the optical path of light passing through the chip.

18. The method of claim 13 , further comprising forming a first waveguide in the chip, wherein the first waveguide is configured to guide light through the etched facet.

19. The method of claim 18 , further comprising forming a second waveguide in the platform, wherein the second waveguide is optically aligned with the first waveguide.

20. A method comprising:
providing a platform, wherein a pit in the platform is defined at least in part by a sidewall and a base;
bonding a chip within the pit to the base of the platform, wherein the chip comprises a side defined in part by a cleaved or diced facet; and
etching a facet in the cleaved or diced facet of the chip to form an etched facet, defining a part of a recess in the side of the chip, after bonding the chip to the platform;
etching the chip to form a first waveguide in the chip, after bonding the chip to the platform, wherein the first waveguide is configured to guide an optical beam along an optical path to pass through the etched facet;
etching the platform to form a second waveguide, after bonding the chip to the platform, wherein the second waveguide is configured to guide the optical beam to pass through the sidewall; and
disposing a contact metal on the chip at a predetermined distance from the etched facet.

Assignees

• Skorpios Tech Inc

Inventors

• Apiratikul Paveen
• Lambert Damien

Classifications

• G02B2006/12061

  Silicon · CPC title

• G02B6/122 Primary

  Basic optical elements, e.g. light-guiding paths · CPC title

• G02B6/136

  by etching · CPC title

• G02B6/1225

  comprising photonic band-gap structures or photonic lattices · CPC title

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title