III-V chip preparation and integration in silicon photonics

Patent metadata

Field	Value
Publication number	US-10312661-B2
Application number	US-201715592704-A
Country	US
Kind code	B2
Filing date	May 11, 2017
Priority date	May 11, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A composite semiconductor laser is made by securing a III-V wafer to a transfer wafer. A substrate of the III-V wafer is removed, and the III-V wafer is etched into a plurality of chips while the III-V wafer is secured to the transfer wafer. The transfer wafer is singulated. A portion of the transfer wafer is used as a handle for bonding the chip in a recess of a silicon device. The chip is used as a gain medium for the semiconductor laser.

First claim

What is claimed is:

1. A method for creating a composite semiconductor laser by bonding a gain chip to a silicon device, the method comprising:
applying an adhesive to a transfer substrate to form a transfer wafer;
securing a device wafer to the transfer wafer by contacting the device wafer to the adhesive;
removing a portion of the device wafer after securing the device wafer to the transfer wafer;
etching trenches in the device wafer to form a plurality of chips, wherein etching trenches is performed after removing the portion of the device wafer;
etching trenches in the transfer substrate to singulate a chip unit, wherein the chip unit comprises:
a chip of the plurality of chips, and
a portion of the transfer wafer;

aligning the chip with a target device after singulating the chip unit, wherein the portion of the transfer wafer is used as a handle to align the chip with the target device;
bonding the chip to the target device; and
removing a portion of the adhesive to disconnect the portion of the transfer wafer from the chip.

2. The method as recited in claim 1 , wherein:
the device wafer is a III-V wafer, and
the target device is a silicon device.

3. The method as recited in claim 1 , wherein:
the target device comprises:
a device substrate comprising silicon, the device substrate forming a floor,
a device layer comprising silicon, wherein:
the device layer forms walls,
a recess in the target device is defined by the floor and the walls, and
an optical waveguide is formed in the device layer;

aligning the chip with the silicon device comprises aligning the chip with the recess of the target device;
the chip comprises:
a facet, and
an active region,

the facet is an etched facet; and
the active region of the chip is optically aligned with the optical waveguide in the device layer such that the composite semiconductor laser is configured to guide an optical beam from the active region of the chip, through the facet of the chip, through a wall of the device layer, and into the optical waveguide.

4. The method as recited in claim 1 , wherein etching the transfer substrate is performed after etching trenches in the device wafer.

5. The method as recited in claim 1 , further comprising forming trenches in the adhesive.

6. The method as recited in claim 1 , wherein:
the device wafer comprises a back side, a front side, and an etch stop dividing the front side from the back side,
the back side is a III-V substrate,
the front side comprises an active region,
the active region is a multi-quantum well structure, and
removing the portion of the device wafer removes the back side of the device wafer.

7. The method of claim 1 , further comprising applying a stop layer, wherein the stop layer is between the transfer substrate and the adhesive.

8. The method of claim 1 , further comprising applying a passivation layer after etching trenches in the device wafer.

9. The method of claim 1 , further comprising applying bond material to pads on the device wafer before singulating the chip unit.

10. The method of claim 1 , wherein the device wafer is a first wafer and the method further comprises:
securing a second wafer to the adhesive,
removing a portion of the second wafer after securing the second wafer to the adhesive, and
etching trenches in the second wafer to form the plurality of chips, wherein etching trenches in the second wafer is performed after removing the portion of the second wafer.

11. A method for creating a composite semiconductor device, the method comprising:
securing a first wafer to a transfer wafer;
securing a second wafer to the transfer wafer;
removing a portion of first wafer;
removing a portion of the second wafer;
etching the first wafer and the second wafer to form a plurality of chips, wherein etching is performed after removing the portion of the first wafer and after removing the portion of the second wafer;
etching the transfer wafer to singulate a chip unit, wherein the chip unit comprises:
a chip of the plurality of chips, and
a portion of the transfer wafer;

bonding the chip to a target device after singulating the chip unit, wherein the portion of the transfer wafer is used as a handle to align the chip with the target device; and
removing the portion of the transfer wafer from the chip.

12. The method of claim 11 , wherein removing the portion of the first wafer and removing the portion of the second wafer are performed concurrently.

13. The method of claim 11 , further comprising forming an optical bridge to optically couple an active region of the chip to a waveguide in the target device.

14. The method of claim 11 , further comprising applying metal to the first wafer and to the second wafer to form under-bump metallization pads on the first wafer and on the second wafer, wherein applying the metal is performed after securing the first wafer and the second wafer to the transfer wafer.

15. The method of claim 11 , further comprising:
applying a dielectric layer to the first wafer, and
securing the first wafer to the transfer wafer by contacting the dielectric layer of the first wafer to an adhesive on the transfer wafer.

Assignees

• Skorpios Tech Inc

Inventors

• Lambert Damien

Classifications

• G02B6/4244

  Mounting of the optical elements · CPC title

• H01S5/0217

  Removal of the substrate · CPC title

• H01S2301/176

  Specific passivation layers on surfaces other than the emission facet · CPC title

• G02B2006/12097

  Ridge, rib or the like · CPC title

• G02B6/136

  by etching · CPC title