Semiconductor test apparatus and semiconductor test method

Patent metadata

Field	Value
Publication number	US-11624767-B2
Application number	US-202117386032-A
Country	US
Kind code	B2
Filing date	Jul 27, 2021
Priority date	Oct 27, 2020
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.

First claim

What is claimed is:

1. A semiconductor test apparatus comprising:
a stage on which a wafer including a plurality of subjects is to be mounted;
a probe card disposed above the stage;
a pressurizing wall disposed on a surface of the probe card opposing the stage, extending toward the stage, and having an opening;
a mark disposed on a lower surface of the pressurizing wall, the lower surface being a surface of the pressurizing wall opposing the stage;
a probe disposed in the opening;
a tube to force air into the opening;
a detector to detect first spacing between a tip of the probe and the mark; and
a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing detected by the detector, wherein
when an electrical property of each of the subjects of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the tube.

2. The semiconductor test apparatus according to claim 1 , further comprising
a movable unit to move at least one of the stage and the probe card in a direction in which the stage and the probe card oppose each other.

3. The semiconductor test apparatus according to claim 1 , wherein
the probe card has a through hole leading to the opening,
the tube is connected to the through hole through a joint, and
an outlet area is smaller than an inlet area, the inlet area being a cross-sectional area of the joint through which the air passes, the outlet area being a product of an inner perimeter of the pressurizing wall and a length from the lower surface of the pressurizing wall to the tip of the probe.

4. The semiconductor test apparatus according to claim 1 , further comprising
an additional tube having one end connected to the opening and the other end connected to a pressure gauge.

5. The semiconductor test apparatus according to claim 1 , further comprising
a pressure sensor disposed in the opening to measure pressure in the opening.

6. The semiconductor test apparatus according to claim 1 , further comprising:
a temperature measurement unit to measure a temperature of the stage; and
an air temperature controller to control a temperature of the air based on the temperature measured by the temperature measurement unit.

7. The semiconductor test apparatus according to claim 1 , wherein
the predetermined spacing is 50 μm to 130 μm.

8. A semiconductor test method of measuring the electrical property of each of the subjects of the wafer using the semiconductor test apparatus according to claim 1 , the semiconductor test method comprising:
(a) mounting the wafer on the stage;
(b) calculating the second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing detected by the detector;
(c) bringing the stage and the probe card into proximity based on the second spacing calculated in the step (b);
(d) forcing the air into the opening through the tube to increase pressure in the opening; and
(e) measuring the electrical property of each of the subjects of the wafer.

Assignees

• Mitsubishi Electric Corp

Inventors

• Takaki Yasushi
• Yamashita Kinya
• Ueno Masaki

Classifications

• G01R31/2601 Primary

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title

• G01R31/12 Primary

  Testing dielectric strength or breakdown voltage {; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing (G01R31/08, G01R31/327 and G01R31/72 take precedence; measuring in plasmas G01R19/0061; measuring dielectric constants G01R27/2617; ESD, EMC or EMP testing of circuits G01R31/002)} · CPC title

• G01R31/26

  Testing of individual semiconductor devices (testing of photovoltaic devices H02S50/10; testing or measuring during manufacture or treatment {H10P74/00}) · CPC title

• G01R31/261

  for measuring break-down voltage or punch through voltage therefor · CPC title

• G01R31/2623

  for measuring break-down voltage therefor · CPC title