Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction

Patent metadata

Field	Value
Publication number	US-11620132-B2
Application number	US-201916406839-A
Country	US
Kind code	B2
Filing date	May 8, 2019
Priority date	May 8, 2019
Publication date	Apr 4, 2023
Grant date	Apr 4, 2023

Abstract

Various embodiments are provided reusing an operand in an instruction set architecture (ISA) by one or more processors in a computing system. An instruction may specify that an operand register for a selected operand retain operand data used by a previous instruction. The operand data in the operand register may be reused by the instruction.

First claim

The invention claimed is:

1. A method for reusing an operand in an instruction set architecture (ISA) by one or more processors in a computing environment, the method comprising:
specifying in an instruction that an operand register for a selected operand retain an input value received from a first-in-first-out (FIFO) source and used by a previous instruction, the retaining performed according to an operand specifier value defined, in a given instruction format of the ISA, in a predefined operand specifier field for the selected operand, wherein the operand specifier value indicates, prior to a first processor cycle during which the instruction is performed, to an operand multiplexer to reuse the input value used by the previous instruction, and wherein, upon receiving the operand specifier value, the operand multiplexer returns the input value used by the previous instruction to the operand register for use by the instruction; and
reusing the input value in the operand register by the instruction.

2. The method of claim 1 , further including retaining the input value in the operand register by one or more subsequent instructions.

3. A system for reusing an operand in an instruction set architecture (ISA) in a computing environment, comprising:
one or more computers with executable instructions that, when executed by a processor of the one or more computers, cause the processor to:
specify in an instruction that an operand register for a selected operand retain an input value received from a first-in-first-out (FIFO) source and used by a previous instruction, the retaining performed according to an operand specifier value defined, in a given instruction format of the ISA, in a predefined operand specifier field for the selected operand, wherein the operand specifier value indicates, prior to a first processor cycle during which the instruction is performed, to an operand multiplexer to reuse the input value used by the previous instruction, and wherein, upon receiving the operand specifier value, the operand multiplexer returns the input value used by the previous instruction to the operand register for use by the instruction; and
reuse the input value in the operand register by the instruction.

4. The system of claim 3 , wherein the executable instructions, when executed by the processor, further cause the processor to retain the input value in the operand register by one or more subsequent instructions.

5. A non-transitory computer-readable storage medium having computer-readable program code portions stored therein for reusing an operand in an instruction set architecture (ISA) in a computing environment, the computer-readable program code portions comprising executable instructions that, when executed by a processor, cause the processor to:
specify in an instruction that an operand register for a selected operand retain an input value received from a first-in-first-out (FIFO) source and used by a previous instruction, the retaining performed according to an operand specifier value defined, in a given instruction format of the ISA, in a predefined operand specifier field for the selected operand, wherein the operand specifier value indicates, prior to a first processor cycle during which the instruction is performed, to an operand multiplexer to reuse the input value used by the previous instruction, and wherein, upon receiving the operand specifier value, the operand multiplexer returns the input value used by the previous instruction to the operand register for use by the instruction; and
reuse the input value in the operand register by the instruction.

6. The non-transitory computer-readable storage medium of claim 5 , wherein the executable instructions, when executed by the processor, cause the processor to further retain the input value in the operand register by one or more subsequent instructions.

7. The non-transitory computer-readable storage medium of claim 5 , wherein the executable instructions, when executed by the processor, cause the processor to further reuse two consecutive values in the operand register by the instruction.

Assignees

• IBM

Inventors

• Fleischer Bruce
• Shukla Sunil
• Srinivasan Vijayalakshmi
• Choi Jungwook

Classifications

• G06F9/3826

  Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title

• G06F9/30185

  according to one or more bits in the instruction, e.g. prefix, sub-opcode · CPC title

• G06F9/30163

  with implied specifier, e.g. top of stack · CPC title

• G06F9/3824 Primary

  Operand accessing · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title