Current consumption controller
US-11860702-B2 · Jan 2, 2024 · US
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Fleischer Bruce patents
Fleischer Bruce is listed as an inventor on 34 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Fleischer Bruce |
| Total patents | 34 |
| First publication | Jun 13, 2019 |
| Latest publication | Jan 2, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Enhanced low precision binary floating-point formatting
US-11775257-B2 · Oct 3, 2023 · US
Sparse systolic array design
US-11669489-B2 · Jun 6, 2023 · US
Sparse systolic array design
US-2023109301-A1 · Apr 6, 2023 · US
Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction
US-11620132-B2 · Apr 4, 2023 · US
Ultra-low precision floating-point fused multiply-accumulate unit
US-11455142-B2 · Sep 27, 2022 · US
Current consumption controller
US-2022187892-A1 · Jun 16, 2022 · US
Reduced precision based programmable and SIMD dataflow architecture
US-11347517-B2 · May 31, 2022 · US
Low latency floating-point division operations
US-11314482-B2 · Apr 26, 2022 · US
Half-precision floating-point arrays at low overhead
US-11281745-B2 · Mar 22, 2022 · US
Recent patents
Latest publications not already listed above.
Floating point computation for hybrid formats
US-2022075595-A1 · Mar 10, 2022 · US
Instruction initialization in a dataflow architecture
US-11223703-B2 · Jan 11, 2022 · US
Facilitating data processing using SIMD reduction operations across SIMD lanes
US-11216281-B2 · Jan 4, 2022 · US
Binary floating-point multiply and scale operation for compute-intensive numerical applications and apparatuses
US-11182127-B2 · Nov 23, 2021 · US
Dynamic fusion based on operand size
US-11157280-B2 · Oct 26, 2021 · US
Loop management in multi-processor dataflow architecture
US-11138010-B1 · Oct 5, 2021 · US
Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures
US-11095313-B2 · Aug 17, 2021 · US
Low latency floating-point division operations
US-2021149633-A1 · May 20, 2021 · US
Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failures
US-2021119646-A1 · Apr 22, 2021 · US
Half-precision floating-point arrays at low overhead
US-2021049230-A1 · Feb 18, 2021 · US
Reduced precision based programmable and simd dataflow architecture
US-2020401413-A1 · Dec 24, 2020 · US
Ultra-low precision floating-point fused multiply-accumulate unit
US-2020387351-A1 · Dec 10, 2020 · US
Facilitating data processing using simd reduction operations across simd lanes
US-2020364056-A1 · Nov 19, 2020 · US
Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components
US-10838868-B2 · Nov 17, 2020 · US
Reusing an operand in an instruction set architecture (isa)
US-2020356371-A1 · Nov 12, 2020 · US
Binary floating-point multiply and scale operation for compute-intensive numerical applications and apparatuses
US-2020310755-A1 · Oct 1, 2020 · US
Instruction initialization in a dataflow architecture
US-2020304598-A1 · Sep 24, 2020 · US
Programmable data delivery to a system of shared processing elements with shared memory
US-2020285579-A1 · Sep 10, 2020 · US
Enhanced low precision binary floating-point formatting
US-2020233642-A1 · Jul 23, 2020 · US
Enhanced low precision binary floating-point formatting
US-10656913-B2 · May 19, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 34 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F7/5443 | 7 |
| G06F7/483 | 7 |
| G06F9/3887 | 6 |
| G06F9/3001 | 6 |
| G06F9/3888 | 4 |