Method to map convolutional layers of deep neural network on a plurality of processing elements with SIMD execution units, private memories, and connected as a 2D systolic processor array
US-12141513-B2 · Nov 12, 2024 · US
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Choi Jungwook patents
Choi Jungwook is listed as an inventor on 45 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Choi Jungwook |
| Total patents | 45 |
| First publication | Nov 30, 2017 |
| Latest publication | Nov 12, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Low precision deep neural network enabled by compensation instructions
US-12056594-B2 · Aug 6, 2024 · US
Compression of fully connected / recurrent layers of deep network(s) through enforcing spatial locality to weight matrices and effecting frequency compression
US-11977974-B2 · May 7, 2024 · US
Hybrid floating point representation for deep learning acceleration
US-11620105-B2 · Apr 4, 2023 · US
Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instruction
US-11620132-B2 · Apr 4, 2023 · US
Statistics-aware weight quantization
US-11551077-B2 · Jan 10, 2023 · US
System-aware selective quantization for performance optimized distributed deep learning
US-11551054-B2 · Jan 10, 2023 · US
Dynamically resizing minibatch in neural network execution
US-11354573-B2 · Jun 7, 2022 · US
Reduced precision based programmable and SIMD dataflow architecture
US-11347517-B2 · May 31, 2022 · US
Robust gradient weight compression schemes for deep learning applications
US-11295208-B2 · Apr 5, 2022 · US
Recent patents
Latest publications not already listed above.
Facilitating neural network efficiency
US-11195096-B2 · Dec 7, 2021 · US
Deep neural network performance analysis on shared memory accelerator systems
US-11188820-B2 · Nov 30, 2021 · US
Loop management in multi-processor dataflow architecture
US-11138010-B1 · Oct 5, 2021 · US
Hybrid floating point representation for deep learning acceleration
US-2021109709-A1 · Apr 15, 2021 · US
Hybrid floating point representation for deep learning acceleration
US-10963219-B2 · Mar 30, 2021 · US
System-aware selective quantization for performance optimized distributed deep learning
US-2021064954-A1 · Mar 4, 2021 · US
Reduced precision based programmable and simd dataflow architecture
US-2020401413-A1 · Dec 24, 2020 · US
Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components
US-10838868-B2 · Nov 17, 2020 · US
Reusing an operand in an instruction set architecture (isa)
US-2020356371-A1 · Nov 12, 2020 · US
Dynamically resizing minibatch in neural network execution
US-2020311536-A1 · Oct 1, 2020 · US
Programmable data delivery to a system of shared processing elements with shared memory
US-2020285579-A1 · Sep 10, 2020 · US
Matrix multiplication on a systolic array
US-10769238-B2 · Sep 8, 2020 · US
Hybrid floating point representation for deep learning acceleration
US-2020249910-A1 · Aug 6, 2020 · US
Adversarial input identification using reduced precision deep neural networks
US-2020226459-A1 · Jul 16, 2020 · US
Deep learning accelerator architecture with chunking GEMM
US-10657442-B2 · May 19, 2020 · US
Method to Map Convolutional Layers of Deep Neural Network on a Plurality of Processing Elements with SIMD Execution Units, Private Memories, and Connected as a 2D Systolic Processor Array
US-2020134105-A1 · Apr 30, 2020 · US
Very low precision floating point representation for deep learning acceleration
US-10592208-B2 · Mar 17, 2020 · US
Processor and memory transparent convolutional lowering and auto zero padding for deep neural network implementations
US-10565285-B2 · Feb 18, 2020 · US
Matrix multiplication on a systolic array
US-2020012706-A1 · Jan 9, 2020 · US
Low precision deep neural network enabled by compensation instructions
US-2020005125-A1 · Jan 2, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 45 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06N3/063 | 23 |
| G06N3/045 | 19 |
| G06N3/0464 | 19 |
| G06N3/08 | 19 |
| G06N3/084 | 14 |