Semiconductor dies having ultra-thin wafer backmetal systems, microelectronic devices containing the same, and associated fabrication methods

Patent metadata

Field	Value
Publication number	US-11616040-B2
Application number	US-202117151356-A
Country	US
Kind code	B2
Filing date	Jan 18, 2021
Priority date	Jul 16, 2019
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.

First claim

What is claimed is:

1. A microelectronic device, comprising:
a semiconductor die having a die frontside and a die backside opposite the die frontside;
a backmetal system, comprising:
a gold-based ohmic bond layer overlying the die backside, and
a silicon (Si) ingress-resistant plated layer overlying the gold-based ohmic bond layer, the Si ingress-resistant plated layer having an average grain size exceeding that of the gold-based ohmic bond layer;
a substrate having an upper surface, wherein at least a portion of the Si ingress-resistant plated layer is disposed between the semiconductor die and the upper surface of the substrate; and
a die bond material bonding the semiconductor die to the upper surface of the substrate.

2. The microelectronic device of claim 1 wherein the die bond material comprises a sintered material.

3. The microelectronic device of claim 1 wherein the semiconductor die has a thickness less than 101.6 microns.

4. The microelectronic device of claim 1 wherein:
the gold-based ohmic bond layer consists essentially of gold, and
the Si ingress-resistant plated layer is predominately composed of gold, silver, palladium, platinum, or a combination thereof, by weight, while having a lower gold content than does the wafer-level gold-based ohmic bond layer.

5. The microelectronic device of claim 1 wherein the second average grain size is at least ten times the first average grain size.

6. The microelectronic device of claim 1 wherein the gold-based ohmic bond layer is formed in direct contact with the die backside; and
wherein the Si ingress-resistant plated layer is formed in direct contact with the gold-based ohmic bond layer.

7. A microelectronic device, comprising:
a semiconductor die having a die frontside and a die backside opposite the die frontside;
a gold-based ohmic bond layer on the die backside, the gold-based ohmic bond layer having a first average grain size and predominately composed of gold, by weight;
a silicon (Si) ingress-resistant plated layer on the wafer-level gold-based ohmic bond layer, wherein the Si ingress-resistant plated layer has a second average grain size exceeding the first average grain size; and
a substrate having an upper surface, wherein at least a portion of the Si ingress-resistant plated layer is disposed between the semiconductor die and the upper surface of the substrate.

8. The microelectronic device of claim 7 wherein the gold-based ohmic bond layer consists essentially of gold.

9. The microelectronic device of claim 7 wherein the Si ingress-resistant plated layer is predominately composed of gold, by weight, while having a lower gold content than does the gold-based ohmic bond layer.

10. The microelectronic device of claim 7 wherein the Si ingress-resistant plated layer is predominately composed of gold, silver, palladium, platinum, or a combination thereof, by weight.

11. The microelectronic device of claim 7 wherein the second average grain size is at least ten times the first average grain size.

12. The microelectronic device of claim 7 wherein the gold-based ohmic bond layer has an average thickness ranging from 1 to 10 kilo angstroms.

13. The microelectronic device of claim 12 wherein:
the gold-based ohmic bond layer has an average thickness ranging from 3 to 5 kilo angstroms; and
the Si ingress-resistant plated layer has an average thickness equal to or greater than the wafer-level gold-based ohmic bond layer.

14. The microelectronic device of claim 7 further comprising:
a substrate; and
a sintered bond layer attaching the semiconductor die to the substrate.

15. A microelectronic device, comprising:
a semiconductor die comprising a die backside, a gold-based ohmic bond layer formed on the die backside, and a silicon (Si) ingress-resistant plated layer formed on the gold-based ohmic bond layer, the Si ingress-resistant plated layer having an average grain size exceeding that of the gold-based ohmic bond layer;
a substrate having an upper surface, wherein at least a portion of the Si ingress-resistant plated layer is disposed between the semiconductor die and the upper surface of the substrate; and
a sintered bond layer contacting the Si ingress-resistant plated layer and bonding the semiconductor die to the substrate.

16. The microelectronic device of claim 15 wherein:
the substrate comprises an electrically conductive base flange;
the semiconductor die comprises a transistor; and
a source region of the transistor is electrically coupled to the electrically-conductive base flange through the gold-based ohmic bond layer, the Si ingress-resistant plated layer, and the sintered bond layer.

17. The microelectronic device of claim 15 wherein the gold-based ohmic bond layer consists essentially of gold.

18. The microelectronic device of claim 15 wherein the Si ingress-resistant plated layer is predominately composed of gold, by weight, while having a lower gold content than does the gold-based ohmic bond layer.

19. The microelectronic device of claim 15 wherein the Si ingress-resistant plated layer is predominately composed of gold, silver, palladium, platinum, or a combination thereof, by weight.

20. The microelectronic device of claim 15 wherein the second average grain size is at least ten times the first average grain size.

Assignees

• Nxp Usa Inc

Inventors

• Sun Tianwei
• Molla Jaynal A

Classifications

• H10W72/551

  Materials of bond wires · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title