Integrator and analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-11611347-B2
Application number	US-202117375803-A
Country	US
Kind code	B2
Filing date	Jul 14, 2021
Priority date	Jul 15, 2020
Publication date	Mar 21, 2023
Grant date	Mar 21, 2023

Abstract

An integrator and an analog-to-digital converter are provided. The analog-to-digital converter includes the integrator, a comparison circuit and a control logic circuit. The integrator includes an operational amplifier, offset capacitors, input capacitors, integral capacitors and controllable switches. The input capacitors and the integral capacitors are connected to the operational amplifier via controllable switches, so that the integrator operates in various operation modes. Operation states of the offset capacitors in a first phase and a second phase of an operation cycle are controlled by switching on or off the controllable switches. Therefore, an offset voltage of the integrator is eliminated, and conversion efficiency and conversion accuracy of the analog-to-digital converter is improved.

First claim

The invention claimed is:

1. An integrator, comprising:
an operational amplifier, wherein the operational amplifier comprises a first input terminal, a second input terminal, a first output terminal and a second output terminal;
a first offset capacitor and a second offset capacitor, wherein the first offset capacitor is coupled to the first input terminal, and the second offset capacitor is coupled to the second input terminal;
a plurality of controllable switches, a plurality of input capacitors and a plurality of integral capacitors, wherein the input capacitors and the integral capacitors are connected to the operational amplifier via the controllable switches, to control an operation mode of the integrator,
wherein the controllable switches are configured to control operation states of the first offset capacitor and the second offset capacitor in a first phase and a second phase of an operation cycle to eliminate an offset voltage of the operational amplifier; and wherein:
the first offset capacitor and the second offset capacitor are configured to store the offset voltage in the first phase; and
the offset voltage of the operational amplifier is eliminated by counteracting the offset voltage with a voltage across the first offset capacitor and a voltage across the second offset capacitor in the second phase.

2. The integrator according to claim 1 , wherein the operation mode of the integrator comprises a return-to-zero mode, a first integral mode and a second integral mode.

3. The integrator according to claim 2 , wherein
the integrator is reset in a first phase of the return-to-zero mode; and
the integrator is configured to, in a second phase of the return-to-zero mode, sample an input voltage signal and output the sampled input voltage signal.

4. The integrator according to claim 2 , wherein
the integrator is configured to, in the first integral mode: sample a reference voltage signal and output an integral signal in a last operation cycle; and sample an input voltage signal and a reference voltage signal and output an integral signal in an operation cycle other than the last operation cycle.

5. The integrator according to claim 2 , wherein in the first integral mode,
an integral signal outputted by the integrator in a last operation cycle is equal to a sum of an integral signal outputted by the integrator in an operation cycle immediately before the last operation cycle and a first signal; and
an integral signal outputted by the integrator in an operation cycle other than the last operation cycle is equal to a sum of an integral signal outputted by the integrator in a previous operation cycle, the first signal and an input voltage signal, wherein the first signal is a product of a reference voltage signal and a first coefficient.

6. The integrator according to claim 5 , wherein
in a case that the integrator is configured to receive a positive reference voltage signal in the first phase and receive a negative reference voltage signal in the second phase, the first coefficient is equal to 1;
in a case that the integrator is configured to receive a negative reference voltage signal in the first phase and receive a positive reference voltage signal in the second phase, the first coefficient is equal to −1; and
in a case that the integrator is configured to receive a zero reference signal in the first phase and the second phase, the first coefficient is equal to 0.

7. The integrator according to claim 2 , wherein the integrator is configured to, in the second integral mode, amplify an output voltage of the integrator in a previous operation cycle.

8. The integrator according to claim 2 , wherein the integrator is configured to, in a first phase of the second integral mode, sample a reference voltage signal and output an integral signal, wherein in a second phase of the second integral mode, an integral signal outputted by the integrator in a current operation cycle is equal to a multiple of a sum of an integral signal outputted by the integrator in an operation cycle immediately before the current operation cycle and a first signal, wherein the first signal is a product of a reference voltage signal and a first coefficient.

9. The integrator according to claim 8 , wherein
in a case that the integrator is configured to receive a positive reference voltage signal in the first phase and receive a negative reference voltage signal in the second phase, the first coefficient is equal to 1;
in a case that the integrator is configured to receive a negative reference voltage signal in the first phase and receive a positive reference voltage signal in the second phase, the first coefficient is equal to −1; and
in a case that the integrator is configured to receive a zero reference signal in the first phase and the second phase, the first coefficient is equal to 0.

10. The integrator according to claim 2 , wherein
the input capacitors comprise a first input capacitor and a second input capacitor, and the integral capacitors comprise a first integral capacitor, a second integral capacitor, a third integral capacitor and a fourth integral capacitor, wherein
the first input capacitor, the first integral capacitor and the second integral capacitor each are configured to be coupled to at least one of the first input terminal and the first output terminal of the operational amplifier, and the second input capacitor, the third integral capacitor and the fourth integral capacitor each are configured to be coupled to at least one of the second input terminal and the second output terminal of the operational amplifier; and
in the second integral mode, the second integral capacitor is configured to charge the first integral capacitor in a current operation cycle, and the first input capacitor is configured to charge the first integral capacitor in an operation cycle immediately after the current operation cycle, and the fourth integral capacitor is configured to charge the third integral capacitor in the current operation cycle and the second input capacitor is configured to charge the third integral capacitor in the operation cycle immediately after the current operation cycle, to amplify an output voltage of the integrator in the current operation cycle.

11. The integrator according to claim 1 , wherein the input capacitors comprise a first input capacitor, a second input capacitor, a third input capacitor and a fourth input capacitor, wherein the first input capacitor and the third input capacitor each are configured to be coupled to the first input terminal of the operational amplifier, and the second input capacitor and the fourth input capacitor each are configured to be coupled to the second input terminal of the operational amplifier, and wherein
the first input capacitor and the second input capacitor are configured to receive an input voltage signal or a common mode voltage signal, and the third input capacitor and the fourth input capacitor are configured to receive a reference voltage signal or a common mode voltage signal.

12. An analog-to-digital converter, comprising:
an integrator comprising an operational amplifier, a plurality of controllable switches and a plurality of capacitors, wherein the operational amplifier comprises a first input terminal, a second input terminal, a first output terminal and a second output terminal, and the capacitors are connected to the operational amplifier via the controllable switches;
a comparison circuit configured to receive an output signal of the integrator; and
a control logic circuit configured to generate a digital signal corresponding to an input voltage signal based on an output signal of the comparison circuit, a

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Huang Ying
• Gao Di
• Li Kun
• Qin Jinyu

Classifications

• H03F2200/264

  An operational amplifier based integrator or transistor based integrator being used in an amplifying circuit · CPC title

• H03M1/403 Primary

  using switched capacitors · CPC title

• H03M1/34

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• H03M1/1285

  Synchronous circular sampling, i.e. using undersampling of periodic input signals · CPC title

• H03M1/1245 Primary

  Details of sampling arrangements or methods · CPC title