Calibrated SAR ADC having a reduced size

Patent metadata

Field	Value
Publication number	US-9319059-B1
Application number	US-201514732676-A
Country	US
Kind code	B1
Filing date	Jun 6, 2015
Priority date	Jun 6, 2015
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) ( 100 ) is substantially reduced by using a number of shared capacitors (SC 1 -SCs−1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.

First claim

What is claimed is:

1. A SAR ADC comprising:
a DAC having a capacitor array, the capacitor array having a plurality of segments, and a number of attenuation capacitors that are connected to the plurality of segments such that an attenuation capacitor is connected to and between each adjacent pair of segments, the plurality of segments including:
a main DAC segment having a number of binary-weighted main conversion capacitors, none of the number of binary-weighted main conversion capacitors having substantially identical weights;
one or more sub-DAC segments having a number of binary-weighted sub-DAC capacitors, one sub-DAC segment having three binary-weighted sub-DAC capacitors that have substantially identical weights;

a comparator connected to the DAC; and
a controller connected to the DAC and the comparator;
wherein the main DAC segment further has a number of main switches that are connected to the binary-weighted main conversion capacitors;

wherein each of the main conversion capacitors has a first plate that is connected to a main node, and a second plate that is connected to a main switch, each main switch to be connected to receive an input voltage, a reference voltage, or ground, and a sequence of control words that each selects the input voltage, the reference voltage, or ground that is to be placed on the second plates of the main conversion capacitors.

2. The SAR ADC of claim 1 wherein the DAC further includes a ground switch that is connected between the main node and ground.

3. The SAR ADC of claim 2 wherein the sub-DAC segments further have a number of sub-switches that are connected to the binary-weighted sub-DAC capacitors.

4. The SAR ADC of claim 3 wherein each of the sub-DAC capacitors has a first plate that is connected to a sub-node, and a second plate that is connected to a sub-switch, each sub-switch to be connected to receive the input voltage, the reference voltage, or ground, and the sequence of control words that each selects the input voltage, the reference voltage, or ground that is to be placed on the second plates of the sub-conversion capacitors.

5. The SAR ADC of claim 4 wherein the controller is connected to the ground switch, the main switches, and the sub-switches.

6. The SAR ADC of claim 5 wherein the plurality of segments are arranged in series.

7. A SAR ADC comprising:
a DAC having a capacitor array, the capacitor array having a plurality of segments, and a number of attenuation capacitors that are connected to the plurality of segments such that an attenuation capacitor is connected to and between each adjacent pair of segments, the plurality of segments including:
a main DAC segment having a number of binary-weighted main conversion capacitors, none of the number of binary-weighted main conversion capacitors having substantially identical weights;
one or more sub-DAC segments having a number of binary-weighted sub-DAC capacitors, one sub-DAC segment having three binary-weighted sub-DAC capacitors that have substantially identical weights;

a comparator connected to the DAC; and
a controller connected to the DAC and the comparator;

further comprising a differential DAC that is connected to the comparator and the controller, the differential DAC having a differential capacitor array, the differential capacitor array having a plurality of differential segments, and a number of differential attenuation capacitors that are connected to the plurality of differential segments such that a differential attenuation capacitor is connected to and between each adjacent pair of differential segments, the plurality of differential segments including:
a differential main DAC segment having a number of binary-weighted differential main conversion capacitors, none of the number of binary-weighted differential main conversion capacitors having substantially identical weights;
one or more differential sub-DAC segments having a number of binary-weighted differential sub-DAC capacitors, one differential sub-DAC segment having three binary-weighted differential sub-DAC capacitors that have substantially identical weights.

8. A method of calibrating a SAR ADC comprising:
closing a ground switch;
connecting a reference voltage to a first selected number of capacitors of a plurality of capacitors, and ground to a first remaining number of capacitors of the plurality of capacitors, the first selected number of capacitors excluding a main conversion capacitor that is being calibrated and any previous main conversion capacitors that have been calibrated, each of the plurality of capacitors having a specified capacitance, a sum of the specified capacitances of the first selected number of capacitors adding up to a first value;
opening the ground switch after the reference voltage has been connected to the first selected number of capacitors, and ground to the first remaining number of capacitors;
connecting the reference voltage to a second selected number of capacitors of the plurality of capacitors, and ground to a second remaining number of capacitors of the plurality of capacitors to generate a first DAC voltage after the ground switch has been opened, the second selected number of capacitors including the main conversion capacitor that is being calibrated, and excluding any previous main conversion capacitors that have been calibrated, a sum of the specified capacitances of the second selected number of capacitors adding up to a second value that is equal to the first value.

9. The method of claim 8 and further comprising comparing the first DAC voltage to a control voltage to determine a first comparison sign.

10. The method of claim 9 and further comprising:
connecting an integer calibration capacitor to ground and a first shared capacitor to the reference voltage when the first comparison sign is positive to generate a second DAC voltage; and
comparing the second DAC voltage to the control voltage to determine a second comparison sign.

11. The method of claim 10 and further comprising:
connecting the first shared capacitor to the reference voltage when the first comparison sign is negative to generate a third DAC voltage; and
comparing the third DAC voltage to the control voltage.

12. A method of operating a SAR ADC comprising:
first determining a logic value for a most significant bit (MSB) within a digital word, the first determining including:
connecting an input voltage to a first plurality of capacitors, the first plurality of capacitors including a plurality of main conversion capacitors, a plurality of sub-conversion capacitors, and a plurality of shared capacitors; and
connecting a reference voltage to a second plurality of capacitors, the second plurality of capacitors including a main conversion capacitor of the plurality of main conversion capacitors, and a first selected number of shared capacitors of the plurality of shared capacitors to generate a MSB DAC voltage; and

second determining a logic value for a least significant bit (LSB) within the digital word, the second determining including connecting the reference voltage to a second selected number of shared capacitors from the plurality of shared capacitors to generate a LSB DAC voltage.

13. The method of claim 12 wherein the first determining further includes comparing the MSB DAC voltage to a control voltage to generate a first comparison sign.

14. The method of claim 13 wherein the first determining further includes connecting the main conversion capacitor to ground, and the reference voltage to a next main conversion capacitor when the first comparison sign is positive.

15. The

Assignees

• Texas Instruments Inc

Inventors

• Sharma Ajit
• Lee Seung Bae
• Ramaswamy Srinath Mathur
• Narayanan Sriram
• Polley Arup

Classifications

• H03M1/46 Primary

  with digital/analogue converter for supplying reference values to converter · CPC title

• H03M1/403

  using switched capacitors · CPC title

• H03M1/1028

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title