Method for forming channels in printed circuit boards by stacking slotted layers

Patent metadata

Field	Value
Publication number	US-11606865-B2
Application number	US-201916678188-A
Country	US
Kind code	B2
Filing date	Nov 8, 2019
Priority date	Nov 8, 2019
Publication date	Mar 14, 2023
Grant date	Mar 14, 2023

Abstract

A process of fabricating an electromagnetic circuit includes providing three laminate sheets, forming a first feature in a first laminate sheet of the three laminate sheets, and forming a second feature in a second laminate sheet of the three laminate sheets. The second feature is aligned with the first feature when aligning the second laminate sheet with the first laminate sheet. The process further includes stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with the third laminate sheet. The first feature and the second feature define a contiguous element. The process further includes filling the contiguous element with an electrically conductive material to form an electrically continuous conductor.

First claim

What is claimed is:

1. A process of fabricating an electromagnetic circuit, the process comprising:
providing three laminate sheets, each laminate sheet including a flat sheet of dielectric material having a layer of copper applied to the sheet, the copper layer being formed into conductive lines and traces, including pads and vias;
forming at least one first feature in a first laminate sheet of the three laminate sheets, the at least one first feature being a slot or channel;
forming at least one second feature in a second laminate sheet of the three laminate sheets, the at least one second feature being a slot or channel, the at least one second feature being aligned with the first feature when aligning the second laminate sheet with the first laminate sheet;
after forming the at least one first feature in the first laminate sheet and the at least one second feature in the second laminate sheet, stacking the three laminate sheets so that the first laminate sheet is positioned above and aligned with the second laminate sheet and the second laminate sheet is positioned above and aligned with a third laminate sheet, the at least one first feature and the at least one second feature defining a contiguous element; and
after stacking the three laminate sheets, filling the contiguous element with an electrically conductive material to form an electrically continuous conductor, the electrically continuous conductor creating a Faraday wall.

2. The process of claim 1 , wherein the third laminate sheet is formed with a solid copper layer to create a ground plane, with the electrically continuous conductor being in contact with the ground plane.

3. The process of claim 1 , wherein the third laminate sheet includes a conductive trace in communication with the contiguous element.

4. The process of claim 1 , wherein the copper layer is etched or milled to form a desired electrical pattern.

5. The process of claim 1 , wherein the laminate sheets are stacked with respect to one another manually with the aid of an alignment fixture having pins.

6. The process of claim 1 , further comprising, after stacking the laminate sheets, curing the laminate sheets under pressure and temperature to form an integral final product having a uniform thickness.

7. The process of claim 1 , wherein filling a channel with an electrically conductive material includes deposition of conductive ink into the channel.

8. The process of claim 1 , further comprising disposing a fourth laminate sheet over the first laminate sheet.

Assignees

• Raytheon Co

Inventors

• Pevzner Mikhail
• Beninati Gregory G
• Benedict James E
• Southworth Andrew R

Classifications

• H05K1/183

  associated with components mounted in and supported by recessed areas of the PCBs · CPC title

• H05K1/092

  Dispersed materials, e.g. conductive pastes or inks · CPC title

• H05K3/4697

  having cavities, e.g. for mounting components (H05K3/4691 takes precedence) · CPC title

• H05K3/4638

  Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits · CPC title

• H05K3/4632

  laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets · CPC title