High performance interconnect

Patent metadata

Field	Value
Publication number	US-11599497-B2
Application number	US-202017008363-A
Country	US
Kind code	B2
Filing date	Aug 31, 2020
Priority date	Mar 3, 2017
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.

First claim

What is claimed is:

1. An apparatus comprising:
a port to couple to a device over an interconnect, wherein the port comprises protocol circuitry to:
send a particular training sequence on the interconnect in association with training of a link on the interconnect, wherein the link is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol, the sent training sequence is a TS2-type training sequence based on the PCIe-based protocol, TS2-type training sequences are defined to comprise a set of symbols and a particular one of the set of symbols comprises bits defined by the PCIe-based protocol to identify whether a number of retimers are present on the link, wherein the particular training sequence is sent in-band on the interconnect;
receive a training sequence on the interconnect during the training of the link, wherein the received training sequence is also a TS2-type training sequence, the bits in the particular symbol of the received training sequence indicate a particular number of retimers present on the link, wherein the particular number of retimers are positioned between the port and the device on the interconnect; and
participate with the number of retimers in equalization of the link during the training of the link, wherein training of the link comprises the equalization of the link, and the equalization of the link is based on the particular number of retimers present on the link.

2. The apparatus of claim 1 , wherein the protocol circuitry is to train the link to operate at a speed of 16.0 gigatransfers/second (GT/s).

3. The apparatus of claim 1 , wherein the PCIe-based protocol comprises PCIe Generation 4.0.

4. The apparatus of claim 1 , wherein the particular symbol comprises symbol 5 of the TS2-type training sequence.

5. The apparatus of claim 1 , wherein the received training sequence is responsive to the sent training sequence.

6. The apparatus of claim 1 , wherein the particular number of retimers comprises zero, one, or two retimers.

7. The apparatus of claim 1 , wherein the protocol circuitry is further to send a SKP ordered set (SKP OS) on the link, and the SKP OS is to be used to perform clock compensation for the link.

8. An apparatus comprising:
a retimer to extend a physical length of a link, wherein the link is to couple a first device to a second device, and the retimer is to be positioned between the first device and second device on the link, wherein the link is compliant with a PCIe-based protocol, and the retimer comprises protocol circuitry to:
receive a first TS2 training sequence sent by the first device on a first link segment of the link, wherein the first link segment connects the first device to the retimer, the first TS2 training sequence is based on the PCIe-based protocol, the first TS2 training sequence comprises a particular symbol, and the particular symbol comprises a set of bits defined by the PCIe-based protocol to identify presence of retimers on the link, wherein the first TS2 training sequence is received in-band on the interconnect;
regenerate the first TS2 training sequence to forward to the second device on a second link segment of the link, wherein the second link segment connects the retimer to the second device, and the first TS2 training sequence is regenerated to include a value in the set of bits to identify presence of the retimer on the link;
send the regenerated first TS2 training sequence to the second device on the second link segment; and
participate in an equalization of the link during training of the link based on the PCIe-based protocol, wherein the training of the link comprises the equalization of the link, and the equalization of the link is based on the presence of retimers on the link.

9. The apparatus of claim 8 , wherein the particular symbol comprises symbol 5 of the first TS2 training sequence.

10. The apparatus of claim 8 , wherein the protocol circuitry is further to:
receive a second TS2 training sequence from the second device over the second link segment, wherein the second TS2 training sequence comprises the particular symbol; and
forward the second TS2 training sequence to the first device over the first link segment, wherein the second TS2 training sequence is a looped-back version of the first TS2 training sequence.

11. The apparatus of claim 10 , wherein the protocol circuitry is further to regenerate the second TS2 training sequence to include a particular value in the set of bits of the particular symbol in the second TS2 training sequence to identify presence of the retimer, and the regenerated second TS2 training sequence is forwarded to the first device.

12. The apparatus of claim 8 , wherein the equalization comprises transmitter equalization at the retimer.

13. The apparatus of claim 8 , wherein the protocol circuitry is further to:
receive an ordered set from the first device on the first link segment; and
identify that the ordered set comprises a SKP ordered set (SKP OS) based on the PCIe-based protocol.

14. The apparatus of claim 13 , wherein the protocol circuitry is further to remove a symbol from the SKP OS to perform clock compensation for the link.

15. A system comprising:
a first device;
a second device; and
a retimer, wherein the first device and the second device are coupled by a physical interconnect, the retimer is positioned between the first device and the second device on the interconnect, the retimer is to extend the physical length of a link to be established on the interconnect, and the first device comprises protocol circuitry to:
send a particular training sequence on the interconnect in association with training of the link, wherein the link is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol, the sent training sequence is a TS2-type training sequence based on the PCIe-based protocol, TS2-type training sequences are defined to comprise a set of symbols and a particular one of the set of symbols comprises bits defined by the PCIe-based protocol to identify whether a number of retimers are present on the link, wherein the particular training sequence is sent in-band on the interconnect;
receive a training sequence on the interconnect during the training of the link, wherein the received training sequence is also a TS2-type training sequence, the bits in the particular symbol of the received training sequence indicate a particular number of retimers present on the link, wherein the particular number of retimers comprise the retimer; and
participate with the number of retimers in equalization of the link during the training of the link, wherein training of the link comprises the equalization of the link, and the equalization of the link is based on the particular number of retimers present on the link.

16. The system of claim 15 , wherein the retimer comprises circuitry to:
receive the particular training sequence from the first device on a first link segment formed on the interconnect to physically couple the first device to the retimer;
set a value in the bits in the particular symbol to identify presence of the retimer on the link;
forward the particular training sequence to the second device on a second link segment, wherein the training sequence forwarded to the second device comprises the value in the bits in the particular symbol, and the second link segment physically connects the retimer to the second device.

17. The system of claim 16 , wherein the particular symbol comprises symbol 5 of a PCIe TS2 training sequence.

18. The system of claim 16 , wherein the P

Assignees

• Intel Corp

Inventors

• Wu Zuoguo
• Das Sharma Debendra
• Mazumder Mohiuddin M
• Guo Jong-Ru
• Sriramulu Anupriya
• Lanka Narasimha
• Wig Timothy
• Morriss Jeff

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• G06F15/16

  Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs {(coordinating program control therefor G06F9/52; in regulating and control system G05B)} · CPC title

• G06F15/17343 Primary

  wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture (reconfigurable processors arrays G06F15/7867) · CPC title

• G06F9/28

  Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel · CPC title