High performance interconnect

Patent metadata

Field	Value
Publication number	US-10789201-B2
Application number	US-201715636738-A
Country	US
Kind code	B2
Filing date	Jun 29, 2017
Priority date	Mar 3, 2017
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.

First claim

What is claimed is:

1. An apparatus comprising:
a receiver to receive one or more training sequences during a training of a point-to-point link, wherein the link is to connect two devices, a first one of the two devices comprises the receiver, and the training is based on a Peripheral Component Interconnect Express (PCIe)-based protocol;
agent logic, at the first device, to:
determine, from a value in a particular symbol of a TS2 training sequence in the one or more training sequences, that a first number of retimer devices are present on the link between the two devices, wherein the TS2 training sequence is based on the PCIe-based protocol, and the particular symbol comprises symbol 5 of the TS2 training sequence; and
determine that a particular number of clock compensation ordered sets are to be sent consecutively on the link based on the first number of retimer devices present on the link; and

a transmitter, at the first device, to: send the particular number of consecutive clock compensation ordered sets on the link,
wherein a different number of clock compensation ordered sets are to be sent on the link when a second number of retimer devices are detected on the link, and the second number is a non-zero number lower than the first number.

2. The apparatus of claim 1 , wherein the first number of clock compensation ordered sets are to be scheduled to be sent at a higher frequency than sending of the different number of clock compensation ordered sets.

3. The apparatus of claim 2 , wherein the different number is lower than the particular number of clock compensation ordered sets.

4. The apparatus of claim 1 , wherein the particular number of clock compensation ordered sets are to be sent consecutively based on determining that the first number of retimer devices exceeds a threshold number, and the second number does not exceed the threshold number.

5. The apparatus of claim 4 , wherein the particular number of clock compensation ordered sets comprises two clock compensation ordered sets sent during a time period, and the different number of clock compensation ordered sets comprises a single clock compensation ordered set to be sent during the time period.

6. The apparatus of claim 1 , wherein the clock compensation ordered set comprises a SKP ordered set.

7. The apparatus of claim 6 , wherein the SKP ordered set is according to the PCIe-based protocol.

8. The apparatus of claim 1 , wherein the value is set in a particular bit within symbol 5 of the TS2 training sequence by at least one of the first number of retimer devices.

9. The apparatus of claim 8 , wherein the maximum number of retimer devices comprises four retimer devices.

10. An apparatus comprising:
a retimer comprising:
retiming logic to forward data received on a link from another device on the link, wherein the link connects two end devices and comprises one or more retimers between the two end devices;
a receiver to receive training sequences during training of the link, wherein the training is based on a Peripheral Component Interconnect Express (PCIe)-based protocol;
protocol logic to modify one or more designated bits within a particular symbol of a TS2 training sequence to indicate presence of the retimer on the link, wherein the TS2 training sequence is based on the PCIe-based protocol, and the particular symbol comprises symbol 5 of the TS2 training sequence; and
clocking circuitry to:
receive a reference clock signal; and
define a clock signal for the retimer based on the reference clock signal; and

clock compensation logic to:
detect a clock difference;
determine a number of symbols to remove from or add to a clock compensation ordered set based on the clock difference;
receive a number of consecutive clock compensation ordered sets on the link, wherein the number of clock compensation ordered sets in the plurality of clock compensation ordered sets originally transmitted on the link by one of the end devices is based at least in part on values of the one or more designated bits; and
remove or add symbols to a particular one of the plurality of clock compensation ordered sets based on the clock difference.

11. The apparatus of claim 10 , wherein the particular clock compensation ordered set comprises a last one of the plurality of clock compensation ordered sets, the clock compensation ordered set is according to a defined format, the defined format designates a subset of symbols of the clock compensation ordered set for removal to achieve clock compensation, and the last clock compensation ordered set is to be used based on the subset of symbols of a prior clock compensation ordered set in the plurality of clock compensation ordered sets having been already moved by another retimer on the link.

12. The apparatus of claim 11 , wherein the clock compensation logic removes symbols from the last clock compensation ordered set based on the clock difference, and the retimer further comprises a transmitter to transmit the last clock compensation ordered set with the removed symbols to another device on the link.

13. The apparatus of claim 11 , wherein the plurality of clock compensation ordered sets comprises two consecutive ordered sets, and the two consecutive ordered sets comprise the last clock compensation ordered set and the prior clock compensation ordered set.

14. The apparatus of claim 13 , wherein the prior clock compensation ordered set comprises a first one of the plurality of clock compensation ordered sets.

15. A system comprising:
a first device;
a second device; and
a plurality of retimer devices positioned between the first and second devices on a link to connect the first and second devices;
wherein the first device comprises logic to:
determine, from a value in a particular symbol of a TS2 training sequence received during training of the link, that the plurality of retimer devices are present on the link and that the plurality of retimer devices comprises a first number of retimer based on one or more values in link training sets set by one or more of the number of retimer devices during the training, wherein the training is based on a Peripheral Component Interconnect Express (PCIe)-based protocol, the TS2 training sequence is based on the PCIe-based protocol, and the particular symbol comprises symbol 5 of the TS2 training sequence;
determine that a particular number of clock compensation ordered sets are to be sent consecutively on the link based on the first number of retimer devices present on the link; and
send the particular number of consecutive clock compensation ordered sets on the link,

wherein a different number of clock compensation ordered sets are to be sent on the link when a second number of retimer devices are detected on the link, and the second number is a non-zero number lower than the first number.

16. The system of claim 15 , wherein each of the plurality of retimer devices is to determine whether to add or remove symbols from the clock compensation ordered sets to remedy a respective clock difference identified at the corresponding retimer device.

17. The system of claim 15 , wherein the first number of retimer devices exceeds a threshold number and the second number of retimer devices does not exceed the threshold number.

18. The system of claim 15 , wherein the clock compensation ordered sets comprise SKP ordered sets.

19. The system of claim 18 , wherein the SKP ordered set is based on the Peripheral Component Interconnect Express (PCIe)-based protocol.

Assignees

• Intel Corp

Inventors

• Wu Zuoguo
• Das Sharma Debendra
• Mazumder Mohiuddin M
• Guo Jong-Ru
• Sriramulu Anupriya
• Lanka Narasimha
• Wig Timothy
• Morriss Jeff

Classifications

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H03K19/17736 Primary

  Structural details of routing resources · CPC title

• G06F15/16

  Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs {(coordinating program control therefor G06F9/52; in regulating and control system G05B)} · CPC title

• G06F9/28

  Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel · CPC title